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  Links:

Greg Holmes' page
Joe Britt's page
Jean-Bernard Emond's page: Manuals + Schematics + EPROM



CMI Series I, II (IIx see below):


Overview:
The CMI (Series I) is based upon the Fairlight QASAR M8 computer architecture with a dual-6800 CPU and shared system RAM. Tony Furse (Creative Strategies) originally developed the QASAR M8 (wire-wrap STTL design), which was reworked by Fairlight (using PCBs). The CMI computer sub-system is also referred to as the "QASAR" and incorporates many of the original cards from the Fairlight QASAR M8 system (some "Q..." cards below). The "QASAR" computer was used in various system configurations (such as the original QASAR, the LIGHTWRITER, and the CMI), each having a unique ROMID (Q,L,V,C,K).
The QASAR has a synchronous 8-Bit data/16-Bit address bus (64KB address space), running at 2MHz with 2 alternating access slots for CPU P1 and P2, i.e. at 1MHz per CPU. (This is possible due to the bus allocation scheme employed by the 6800 and later on by the 6809.) DMA accesses by peripheral devices also employ this time-slot scheme, with a separate DMA arbitration chain per CPU. Compared to the QASAR M8 (with Q025 16KB System RAM boards), the CMI QASAR offers paged virtual memory support (MMU contained on the 64KB System RAM board Q096).
As the main difference to the QASAR M8, the CMI Series I/II sound generation and sampling sub-system is a new design and was developed by Peter Vogel.
QASAR M8 and Fairlight CMI sound generation:
The QASAR M8 uses a sound generator system which is distributed over 12 cards for 8 channels of sample-output. It uses a shared 4KB sound RAM (32 segments of 128 8-Bit samples each) which is part of the QASAR system RAM.
In contrast to this, the CMI employs a separate 16KB waveform RAM for each of its 8 channels of sample-playback. Here, each channel together with its own waveform RAM plus address-generator is contained on a separate channel card. Sample values are stored as linearly encoded 8-Bit words. Pitch control is based upon a variable sample-output rate. The CMI channel card also incorporates ramp-generators and a timer. Analog post-processing is provided via a VCF/VCA circuit on each channel card.
Real-time event control (sequencers and keyboard-input handling), real-time sound-generation control (channel-card control, e.g. envelopes), and sampling is accomplished via QASAR CPU P1, whereas the operating system (QDOS) with the user-interface runs on CPU P2. The master card timer and the 8 channel timers are employed for the real-time functions on CPU P1.
The main differences between Series I and II are the improved channel cards (CMI-01 to CMI-01-A with extended pitch-range by 1 oct.), increased sample-rate, and an extended software (e.g. Page R).
Sample output principle:
Variable sample output rate for pitch variation by use of 12-Bit Bit-rate-multipliers (BRM) and frequency dividers. Two sample playback modes: "sampler" Mode 4 and "wavetable synthesizer" Mode 1, see Greg Holmes' infos for more.
* In Mode 1, 32 segments with 128 samples each are used (i.e. only 4KB waveform RAM used). Each segment is looped for a specific amount of time given by a duration-curve (i.e. a function: segment number -> time). The segment number is incremented successively in time steps according to the duration-curve. Additionally, an outer loop can be defined, which repeats a certain sub-set of segments within this segement-sequence. Basically, Mode 1 resembles the possibilities of a QASAR M8.
* In Mode 4, all samples of the 16KB waveform RAM are played linearly (16KB=128 segments x 128 samples). This mode corresponds to a simple sample-player. Here, a single play-back loop can be defined. Sounds are sampled to Mode 4 and can be converted into Mode 1.
Sampling:

The voice master module (CMI-02) is employed for analog sample-input, using CPU P1 for the data transfer from the ADC (on CMI-02) to the sound RAM (on CMI-01(-A)), making use of the CPU-halting logic for synchronization purposes. The CMI Series I offers a max. sample-input rate of 24kHz, whereas the Series II (and Series IIx, see below) provides 30.2kHz.

mainframe boards:

CMI-02 channel master, (34.291712MHz master oscillator, 2x7497 master tuning sample clock generator, AD571JN 10-Bit sample-input ADC, ADC-clock from channel card 1, 2xAD7523JN 8-Bit DACs for sample input VCF/VCA, P1 8214 high-priority PICU, 68B21 channel mask+tuning PIA, 68B21 level+filter control PIA, 68B40 master timer, WRAM timing logic (for CMI-01), different revisions for Series I/II/IIx)
CMI-08 MIDI interface (68B09, 16KB private RAM)
CMI-01 Series I channel output (1 channel, private 16KB waveform RAM, refresh logic, sample-rate generator, address-generator, ramp-generator, 8-Bit sample-out DAC, CV-DACs for VCF/VCA, CEM3320 VCF/VCA, 1 trimmer)
CMI-01-A Series II/IIx channel output (1 channel, extended playback pitch range (1 octave higher), private 16KB waveform RAM, refresh logic, 2x7497 + 74LS393 sample-rate generator, address-generator, ramp-generator, 1x68B40 channel timer, 2x68B21 registers, AD558JN 8-Bit DAC, AD7533JN 8-Bit sample-out DAC, 2xAD7523JN 8-Bit CV-DACs for VCF/VCA, CEM3320 (Rev1,2) or SSM2045 (Rev3,4) VCF/VCA, 7 trimmers)
CMI-07 analog interface ("AIC09", 16 analog inputs and outputs, thought as control voltages for use with analog synthesizers, 6809, 16KB private RAM, 6840, AD565 14-Bit DAC, AD574 14-Bit ADC, 4xAD7524 DAC, 4xAD7501 analog MUX)
Q148 light-pen controller (selectable sync source: Q045/TVT/external)
Q014 4-port ACIA (4x6850 ACIAs, 3x6840 Baud-rate timers, optional 6859 DES crypt)
Q096 System RAM module with MMU (64KB DRAM, 4 card ID switches)
Q032 CPU control module ("Debug Card", ROMs, SRAMs, ACIAs (esp. keyboard I/O), 16-Bit PIA, PICUs)
Q026 Main CPU module (2x6800 @1MHz interleaved on 2MHz QASAR 8-Bit/16-Bit data/address Bus, timing and memory control logic)
QFC2 8" floppy controller (FD1771)
Q045 graphics display card (video output, uses private Q025 with base 0000 as VRAM, x/y autoincrement/decrement Byte/Bit "vector accelerator", CPU select via jumpers: normally P2)
Q025 System RAM module (16KB DRAM, read/write Bit-mask, switchable to base 0000/4000/8000/C000)
Q050 dual-TVT card (P1 peripheral, D000-DFFF)

CMI-05 mainboard
CMI-04 audio board, mixer, power amplifier
Q036 front panel card (with variable Baud-rate generator)

music keyboard:
CMI-10 master music keyboard CPU/interface module (6802, music event data and Alpha keyboard data (RS232) multiplexed, connected to DIN and KEYB DATA OUT (to/from Q032 ACIA (IIx:Q133 SACIA)), 3xCMI-11 attached, external connection to CMI-14 in optional slave keyboard)
CMI-12 master music keyboard display+keypad module
CMI-14 slave music keyboard interface (in slave keyboard, 3xCMI-11 attached, external connection to CMI-10 in master keyboard)
CMI-11 music keyboard switch module (3xCMI-11 in each master and slave keyboard)

card cage:
backplane = CMI-05
1: CMI-02
2: CMI-?, CMI-08
3: CMI-01 (I), CMI-01-A (II)
4: CMI-01 (I), CMI-01-A (II)
5: CMI-01 (I), CMI-01-A (II)
6: CMI-01 (I), CMI-01-A (II)
7: CMI-01 (I), CMI-01-A (II)
8: CMI-01 (I), CMI-01-A (II)
9: CMI-01 (I), CMI-01-A (II)
10: CMI-01 (I), CMI-01-A (II)
11: CMI-07
12: Q148
13: Q096 (card 2)
14: Q096 (card 1)
15: Q096 (card 0)
16: Q032
17: Q026
18: QFC2
19: Q045
20: Q025


Q096 System RAM for QASAR
The QASAR memory management uses a 64KB virtual address space (16 Bits) and typically 64KB physical memory (1xQ096) with 16KB page-size (also called blocks or chunks). The QASAR Bus is synchronous and carries virtual addresses (16-Bit). The memory management units (MMU) are contained on the RAM boards (Q096). This has the advantage that DMA employs the same MMUs as the CPUs.
The Q096 provides a 1-stage address-translation via a MAPRAM which uses 4 separate memory-maps: two CPU time-slots on the QASAR-Bus with two modes A/B each: P1A, P1B, P2A, P2B. Each CPU has a separate mode A/B line, which normally is pulled high (=map A) and can be pulled low (=map B) for map-switching by peripherals. (Also used with earlier Q209 for system/user mode, see Series IIx below.)
The QASAR provides no hardware protection mechanisms (such as page access and CPU instructions) except of a simple write protection (on Q096). Peripheral devices attached to the QASAR Bus employ a memory-mapped I/O concept, appearing at pre-defined virtual addresses. Note that the upper 4KB (Fxxx) virtual address range on the Q096 is deactivated by the Q032 (via RAMINH) since peripheral devices, ROMs and SRAM appear in this region. If the Q045-disable Bit (in CMI-02 register) is cleared, access to the Q045 (esp. VRAM) is enabled and Q096 map B for P2 is selected (AB2 line). (Note that CPU P1 access to the Q045 VRAM is always inhibited.) When using peripheral devices within the address range C000-EFFF (e.g. CMI-02, CMI-01, Q148, TVT), the corresponding page within the Q096 MMU must be explicitely disabled (no automatic hardware deactivation).
Note that in other QASAR system configurations, the actual map select signals might have different assigments, especially regarding the activation of the VRAM for each CPU. For non-CMI QASAR systems (with ROMID Q,L,V), CPU P1 has access to the VRAM for both maps, whereas CPU P2 does not have any access to the VRAM for such a system. The following memory maps are valid for standard CMI systems (with ROMID C,K) as described above.
16KB page size => 4 pages per 64KB virtual (CPU) address space.
upper 2 Bits are the virtual page number, lower 14 Bits are the address within the page.
The MAPRAM supports 15 usable Q096 card IDs. However, the CMI-backplane offers only 3 Q096 slots, thus providing a max. physical RAM of 192KB in a QASAR system (typically, only one Q096 card is used with the CMI).

MAPRAM: memory mapping (on Q096):
access via *(FC40+X)=Y for mapping X -> Y with:
X Bit0-1 = virtual page number
X Bit2 = CPU P1/P2
X Bit3 = mode A/B (separate line per CPU)
Y Bit0 = physical RAM page write enable
Y Bit1-2 = physical RAM page number
Y Bit4-7 = RAM card number (card #F = not used)
Each Q096 contains 4 physical pages of RAM (i.e. 4x16KB).
DRAM refresh is implemented as a dummy P1-DMA access, initiated by a timer on Q032.

Typical CMI virtual address mapping:
CPU P1 (always map A):
0000-3FFF: RAM (Q096)
4000-7FFF: RAM (Q096)
8000-BFFF: RAM (Q096)
C000-CFFF: unused
D000-DFFF: TVT (optional)
E000-FFFF: peripheral devices, ROM, SRAM
CPU P2 (map selected via CMI-02 Q045-disable-Bit):
0000-3FFF: RAM (Q096)
4000-7FFF: RAM (Q096)
8000-BFFF: map B: VRAM (Q045+Q025), map A: RAM (Q096)
C000-CFFF: unused
D000-DFFF: unused
E000-FFFF: peripheral devices, ROM, SRAM
Note: Running QDOS, CPU P2 has two different physical Q096 pages mapped to virtual addresses 0000-3FFF: map A contains the QDOS system, map B contains P2 IOPACK code.


6800 peripheral device address map (RAM disabled for Fxxx via RAMINH):
(8000-BFFF: video RAM, on Q045's private Q025)
(D000-DFFF: CPU P1 only, Q050 TVT hardware)
E000-E03F: channel hardware (CMI-02, CMI-01)
E2D0-E2DF: Q148 lightpen controller
F000-F3FF: ROM (debug monitor, shared, on Q032)
F400-F7FF: ROM (I/O functions, shared, on Q032)
F800-FBFF: ROM (P1:startup+clock, P2:boot+controller, 2xCPU unique, on Q032)
FC00-FCFF: peripherals:
. FC00-FC3F: Q014
. FC40-FC4F: MAPRAM (on Q096)
. FC5A-FC5B: Q077 data/address/status register
. FC5E-FC5F: processor system control (on Q032)
. FCD0-FCDF: Q045 graphics controller
. FCE0-FCE7: QFC2 floppy controller
. FCF0: serial I/O control latch (on Q032)
. FCF4-FCF5: ACIA (on Q032, baud-rate via Q036)
. FCF8-FCFB: PIA (on Q032)
. FCFC: CPU P1 PICU (on Q032)
. FCFD: CPU P2 PICU (on Q032)
FD00-FEFF: SRAM (shared, in Q032)
FF00-FFFF: SRAM (2xCPU unique, on Q032)


6800 interrupt vectors (contained in CPU unique SRAM/ROM on Q032, PICU = "peripheral interrupt controller unit"):
FFFE-FFFF: restart (mirrored from ROM)
FFFC-FFFD: NMI
FFFA-FFFB: SWI
FFF8-FFF9: unused (original IRQ, mapped by PICU)
FFF6-FFF7: unused
FFF4-FFF5: unused
FFF2-FFF3: unused
FFF0-FFF1: unused
FFEE-FFEF: IRQ7 -- 8 prioritized interrupts (high priority PICU)
FFEC-FFED: IRQ6
FFEA-FFEB: IRQ5
FFE8-FFE9: IRQ4
FFE6-FFE7: IRQ3
FFE4-FFE5: IRQ2
FFE2-FFE3: IRQ1
FFE0-FFE1: IRQ0 --
FFDE-FFDF: IRQ15 -- 8 prioritized interrupts (low priority PICU)
FFDC-FFDD: IRQ14
FFDA-FFDB: IRQ13
FFD8-FFD9: IRQ12
FFD6-FFD7: IRQ11
FFD4-FFD5: IRQ10
FFD2-FFD3: IRQ9
FFD0-FFD1: IRQ8 --

The original IRQ interrupt is mapped to 8(16) prioritized interrupts by an Intel 8214 PICU per CPU (16 by cascading two PICUs).
The P2 IRQ is split into 8 interrupts by one PICU (Q032, P2 IRQ0-7). The P1 IRQ is split by a Q032 PICU (low priority P1 IRQ8-15, XIRQ output) and a CMI-02 PICU (high priority P1 IRQ0-7, XIRQ PICU chain input) into 16 interrupts. (Note: the QASAR M8 does not have the second P1 CMI-02 PICU, thus having only 8 interrupts per CPU).


peripheral device interrupts:
CPU P1
0: IRQSYN (Q032, ACIA)
1: TIMER1 (CMI-02, master card timer)
2: P1IR2 (CMI-02, IPI)
3: P1IR10 unused
4: P1IR11 unused
5: unused
6: unused
7: unused
8: CHINT2 (CMI-01, channel timer)
9: CHINT4 (CMI-01, channel timer)
10: CHINT6 (CMI-01, channel timer)
11: CHINT8 (CMI-01, channel timer)
12: CHINT1 (CMI-01, channel timer)
13: CHINT3 (CMI-01, channel timer)
14: CHINT5 (CMI-01, channel timer)
15: CHINT7 (CMI-01, channel timer)
CPU P2:
0: IRQD (QFC2)
1: RINT (Q148)
2: P2IR2 (CMI-02, IPI)
3: unused
4: TOUCHINT (Q148)
5: PENINT (Q148)
6: ADINT (CMI-02, master card ADC)
7: unused


DMA priorities:
(chain ENL(level n) -> ETL(level n+1))
CPU P1:
0 (ENL source for 1): Q032 internal
1: RAM refresh on Q032
CPU P2:
0 (ENL source for 1): "EDL" (from QFC2)
1: QFC2

DMA note: The DMA arbitration is implemented as a priority chain logic (ETL-ENL), distributed over the participating controller cards (and not as a centralized arbiter). Each CPU (Q026 P1/P2) has its independent DMA system. In order to avoid race-conditions with the DMA priority-chain logic, each controller latches its DMA request with the QASAR bus clock P202 (slight delays or differences are uncritical at this point) and asserts the DMA request line (for the required CPU). After a well defined delay (with respect to P202), which ensures that the DMA priority-chain logic has settled, the CPU asserts the acknowledge line, which in turn is used by the (now known) highest-priority controller to start its DMA and especially to sets its required mode line (maps A/B see Q096 MMU). Lower-priority controllers must wait until the next clock phase for new DMA arbitration. Normally, the source of the DMA-priority chain (EDL) is the CPU clock divided by two, in order to have at least every second slot for its CPU. The QASAR bus is clocked by 2MHz, giving 1MHz per CPU and hence 500kHz for DMA per CPU.


Q050 TVT ("text video terminal"):
QASAR addresses:
D000-DFFF (CPU P1 only, screen RAM, "Z.TVTS" to "Z.TVTE"-1)
.D000-D7FF ("TVT", screen 1)
.D800-DFFF ("TVT2", screen 2)
FDFF ("TVTPORT")
FE18 (OS9: "/tvt")
FE19 (OS9: "/tvt2")
FE1D (OS9: "/video", "/vid" (console))
FE72 ("TOFLAG")
FE78 (TVT control block):
.FE78 ("TV.Scrn", screen RAM start address)
.FE7A ("TV.Stat", status)
.FE7B ("TV.TopS"="Z.TOPSCR", top of scroll line)
.FE7C ("TV.Lines"="Z.BOTSCR", lines per screen)
.FE7D ("TV.Chars"="Z.SIDSCR", characters per line)
.FE7E ("TV.CurL", current line)
.FE7F
("TV.CurC", current character position)
FEFE ("TVT_FLAG", if character pending in TVT_CHAR)
FEFF ("TVT_CHAR", output character)
Note: character-based terminal output, two screens with 25 lines and 80 characters per line each, originally implemented as "dual-TVT" card for QASAR (P1 peripheral device), later extended/emulated by MDR display-page (jsys "TVT-Driver", see MFX1/2 below). Often used for debugging purposes.


Q045 graphics card:
A line contains 512 visible Bits (=64 Bytes), with a total of 256 visible lines. The horizontal direction is called y (!) and the vertical direction is x (!), with (0,0) in the upper left corner of the screen. Video output is in CCIR B/W format (625 lines, f_V=50Hz, f_H=15625Hz).
The Q045 card uses a private Q025 RAM card as the Bit-addressable video DRAM which is organized as 8x16K Bits.
The VRAM can be directly accessed from CPU P2 as a 16KByte region in the address range $8000-$BFFF (if CMI-02 Q045-disable-Bit is cleared, see also Q096).
The Q045 furthermore contains a x/y Bit position register ("current position") with auto-increment and -decrement "vector acceleration" functions (mod 256 and mod 512 for x and y, respectively). Reading/writing within $FCD0-$FCDB makes use of these vector acceleration for Bit/Byte access to the VRAM:
FCD0: Bit (x,y)
FCD1: Bit (x,y++)
FCD2: Bit (x,y--)
FCD3: Byte (x,y)
FCD4: Bit (x++,y)
FCD5: Bit (x++,y++)
FCD6: Bit (x++,y--)
FCD7: Byte (x++,y)
FCD8: Bit (x--,y)
FCD9: Bit (x--,y++)
FCDA: Bit (x--,y--)
FCDB: Byte (x--,y)
(where (x,y) is the current Bit position register, and "Byte" mode means 8 Bits from 8*(y/8),...,8*(y/8)+7). Note that access to $8000-$BFFF sets the current position register to the first Bit of the Byte in VRAM.
An 8-Bit "scroll register" (93L08) at $FCDC is used as an x-offset (vertical!) in the readout cycle in order to implement a hardware acceleration of vertical text scrolling.

QASAR addresses:
8000-BFFF: VRAM direct access (P2 only)
FCD0-FCDB: graphics accelerator access ports
FCDC: vertical scroll latch
(Note: CMI-02 Q045-disable-Bit must be cleared for access)


Q148 light pen card:
QASAR addresses:
E2D0-E2D7: PIA (light pen control, status and position)
E2D8-E2DF: timer


master card/channel cards (CMI-02, CMI-01, CMI-01-A):
QASAR addresses:
E000-E03F:
. E000-E01F: CMI-01 (depending on channel mask)
. E020-E023: master card channel mask and master tuning PIA
. E024-E025: sample input ADC
. E026: halt P1
. E027: unhalt P1
. E028-E02B: master card sample input level and filter control PIA
. E030: master card PICU (P1 IRQ0-7)
. E031: set INTP1
. E032: clear INTP1
. E033: set INTP2
. E034: clear INTP2
. E038-E03F: master card timer
(Note: CB2 from PIA at E020-E023 is Q045-disable-Bit and also CPU P2 map select (Q096 AB2))
(Note: in Series IIx with Q256: PENB must be active for access)


floppy and harddisk drives:
see software chapter




CMI Series IIx:


Overview:
Based upon Series II. New dual-6809 QASAR with extended virtual memory and DMA support (Q209, Q133, Q256). New front panel and backplane: Q137, CMI-25. New graphics/light pen controller: Q219. Optional MIDI/SMPTE card: CMI-28 (plus CMI-29 support card). New software (with 6809 QDOS version). For further infos see Greg Holmes' page.
The QASAR-6809 was developed by Peter Vogel. The CMI-28 MIDI/SMPTE card was developed by Peter S. Farleigh.
Comparison with Series I/II:
Series I/II machines have a dual-6800 system with 64KB system RAM, whereas the Series IIx has a dual-6809 with 256KB system RAM with new MMU. (However, early Q209 versions are able to run with Q032 + Q096 cards, see Series II.) The old graphics system plus lightpen logic (Q045, Q025, Q148) has been improved and integrated into one card (Q219) with the Series IIx. However, the Series IIx system has the same channel cards as employed in Series II machines (CMI-01-A).
Comparison with Series III:
The Series IIx and III have the same dual-6809 QASAR computer architecture, same graphics card, and both use the MIDI/SMPTE general interface processor (CMI-28, 68000). However, the channel hardware is completely different: Series IIx with 8 channels with 8-Bit separate 16KB waveform memory vs. Series III with 16 channels with 16-Bit shared 14/32MB waveform memory. Furthermore, instead of QDOS, Series III machines run on a QASAR version of OS-9/6809 Level 2. See Series III below for more details.

mainframe boards:
CMI-02 see Series II
CMI-08 see Series II
CMI-28 SMIDI general interface ("SMIDI" or "MP", MIDI + SMPTE + clock, 68000 @10MHz, 16-128KB private 16-Bit RAM, requires CMI-25 Rev3)
CMI-01-A see Series II
CMI-07 see Series II
Q096 only for Series I/II
Q256 System RAM with MMU and parity (256KB, 3 card ID switches for up to 8 cards)
Q014 see Series II (OS9: "/t0"..."/t3")
Q133 CPU control board (ROMs, SRAMs, clock, ACIAs (esp. keyboard I/O) "SACIA", 16-Bit PIA output, P1/P2 8214 PICUs, system DRAM refresh)
Q209 Main CPU module (P1/P2: 2x6809 @1MHz interleaved on 2MHz QASAR 8-Bit/16-Bit data/address Bus, 40.210MHz master clock)
Q219 graphics and light-pen interface (512x256 monochrome, 16KB video RAM, x/y autoincrement/decrement Byte/Bit "vector accelerator", FIFO for VRAM readout rate conversion, 15625kHz/50Hz B/W video output, light pen decoder, type 'M' in MFX1/2)
QFC9 8" floppy controller (WD1791 controller + FDC9229B PLL)
Q077, Q087 harddisk/tape interface (8-Bit DMA interface, to be connected to a WD1002-05 Winchester controller, OS9 devices "/wdv0" and "/wdv1")

CMI-25 mainboard
Q137 front panel (with hidden serial I/O connector)
CMI-04 see Series II
CMI-29 general interface support (frontend for CMI-28)
QPSA power supply


card cage:
backplane = CMI-25
1: CMI-02
2: CMI-08, CMI-28
3: CMI-01-A
4: CMI-01-A
5: CMI-01-A
6: CMI-01-A
7: CMI-01-A
8: CMI-01-A
9: CMI-01-A
10: CMI-01-A
11: CMI-07
12: Q096 (not supported in Series IIx)
13: Q256 (card 1)
14: Q256 (card 0)
15: Q014
16: Q133
17: Q209
18: Q219
19: QFC9
20: Q077


Q256 System RAM for QASAR-6809:
The QASAR-6809 memory management is different from the QASAR-6800 system (used in Series I/II). It uses a 64KB virtual address space (16 Bits) and up to 2MB physical memory (21 Bits, 8xQ256) with 2KB page-size (optionally 4KB). The QASAR Bus is synchronous and carries virtual addresses (16-Bit). The memory management units (MMU) are contained on the RAM boards (Q256). This has the advantage that DMA channels employ the same MMUs as the CPUs. The Q256 provides a 2-stage address-translation (see below) where each CPU and DMA channel has a separate hardware memory map number. The QASAR provides no hardware protection mechanisms (such as page access and CPU instructions). Peripheral devices attached to the QASAR Bus employ a memory-mapped I/O concept, appearing at pre-defined virtual addresses (enabled via VENB and PENB MMU-Bits, see below).
2KB page size => 32 pages per 64KB virtual (CPU) address space:
upper 5 Bits are the virtual page number, lower 11 Bits are the address within the page.
12 "states" for physical memory access (two time-slots P1/P2 on synchronous QASAR Bus, each CPU P1,P2 has a dedicated state Flip-Flop: two states A and B; there are 4 DMA channels per slot; DMA implies state A):
P1 time-slot:
- CPU P1 state B (user)
- CPU P1 state A (system)
- P1 DMA 1
- P1 DMA 2
- P1 DMA 3
- P1 DMA 4
P2 time-slot:
- CPU P2 state B (user)
- CPU P2 state A (system)
- P2 DMA 1
- P2 DMA 2
- P2 DMA 3
- P2 DMA 4
these 12 states may have separate memory maps.
2-stage translation:
state -> map number
virtual page number & map number -> physical page number (or peripheral device)

1) MAPSEL RAM contains the mapping:
state (4-Bit encoded) -> map number (5-Bit)
therefore we have access to 32 maps (has nothing to do with the 32 virtual pages above!). Such a hardware map number is also called "hardware task number", offering the possibility to store memory mappings of multiple OS9 tasks and system/DMA mappings in harware to accelerate map switching.
MAPSEL also has additional output lines:
- PENB for the memory mapped I/O peripheral devices (D000-E7FF, F000-FFFF),
- VENB for the video RAM (on Q219, 8000-BFFF),
- parity system test line.
The enable lines make devices appear in certain regions of the virtual address space instead of system RAM physical pages (in this case care must be taken to set the "page enable" Bits to 0 for the pages corresponding to these regions; see MAP below.)
Note: on restart, PENB is hardware-activated to ensure access to ROMs/SRAMs and peripheral devices for system setup.

2) MAP RAM contains all the maps:
virtual page number (5-Bit) & map number (5-Bit) -> physical page number (7-Bit for Q256) and CSEL "page enable" Bit (1-Bit)
Q256: 7-Bit + lower 11-Bit form 18-Bit physical address (256KB)
Q356: 4xQ256 on one board
The MAP RAM is also called "Dynamic Address Translator" ("DAT"). The CSEL Bit determines which Q256 board actually contains the physical page for a given virtual page number and map number. Each Q256 has a unique 3-Bit ID (via jumpers), which provides a mechanism to ensures that at most one Q256 has CSEL=1 for a given physical page number. (Note that the MAPSEL RAMs on all Q256s must contain the same information, whereas the MAP RAMs may differ in CSEL for each physical page.) This gives a total of 2MB (8x256KB, 18+3=21 Bits) physical memory space.
Note:
If the selected map (see MAPSEL above) has PENB active, CSEL must be 0 for the device memory regions. But, if VBEN is active in the selected map and a direct access to the VRAM (8000-BFFF) occurs, the Q219 automatically inhibts the Q256s via RAMINH (conntected to Q219 output VRAMSEL), therefore eliminating the necessity to deactivate CSEL for 8000-BFFF in this case.
Note: Access to MAP and MAPSEL RAM via peripheral address windows: F000-F7FF and FC40-FC4F (see below), respectively. QASAR-6809 operating systems normally maintain an image of the written MAP RAM values at E800-EFFF in system virtual space.
Note
: DRAM refresh is accomplished by a timer/counter on Q133 requesting a P1 DMA and issuing the dummy refresh address with VMA=0 ("valid memory address").

Summary:
page size: 2KB (11 Bits)
virtual address space: 64KB (32 pages, 16 Bits)
physical address space: 2MB (1024 pages, 21 Bits)
hardware maps ("tasks"): 32
states: 12
(compare with Tandy CoCo3:
page size: 8KB (13 Bits)
virtual address space: 64KB (8 pages, 16 Bits)
physical address space: 512KB (64 pages, 19 Bits)
hardware maps ("tasks"): 2
)


6809 peripheral device address map (PENB active):
(8000-BFFF: Q219/CG1/CG2/CG3 video RAM via VBEN, not PENB!)
(D000-DFFF: CPU P1 only, Q050 TVT hardware)
E000-E7FF: channel hardware (CMI-02, CMI-01)
(E800-EFFF: no peripheral devices!, typ. MAP RAM image in system space)
F000-F7FF: read: ROM0 (on Q133, shared), write: MAP RAM (on Q256)
F800-FBFF: ROM1 (on Q133, 2xCPU unique)
FC00-FCFF: peripherals:
. FC00-FC3F: Q014 (OS9: /t0, /t1, /t2, /t3)
. FC40-FC4F: write: MAPSEL RAM (on Q256), or MAPRAM (on Q096)
. FC5A-FC5B: Q077 data/address/status register (OS9: /wdc0, /wdc1)
. FC5C: CMI-33, CMI-41 (see Series III)
. FC5E-FC5F: processor system control (on Q133)
. FC70-FC71: QFC9 "Mini-Floppy" (OS9: /m0, /m1, /mh0, /mh1)
. FC80-FC8F: ACIAs (on Q133)
. FC90-FC97: timer (on Q133)
. FCA0: CMI-28
. FCBx: CMI-07 (x=C,D,E,F via 2 jumpers)
. FCC0-FCDF: Q219, CG1/CG2/CG3 (see MFX1/MFX2)
. FCE0-FCE1: QFC9
. FCE2-FCE3: Q777 (see Series III)
. FCF0-FCFF: PIA registers, user and clock (on Q133)
. FCFC: CPU P1 PICU (on Q133)
. FCFD: CPU P2 PICU (on Q133)
FD00-FEFF: SRAM (on Q133, shared)
FF00-FFFF: SRAM (on Q133, 2xCPU unique)
Note: on restart, PENB is hardware-activated to ensure access to ROMs/SRAMs and peripheral devices for system setup.


6809 interrupt vectors (contained in CPU unique SRAM/ROM on Q133, PICU = "peripheral interrupt controller unit"):
FFFE-FFFF: restart (mirrored from FBFE-FBFF on ROM1 via ROMEN)
FFFC-FFFD: NMI
FFFA-FFFB: SWI1
FFF8-FFF9: unused (original IRQ, mapped by PICUs)
FFF6-FFF7: FIRQ
FFF4-FFF5: SWI2
FFF2-FFF3: SWI3
FFF0-FFF1: unused
FFEE-FFEF: IRQ7 -- 8 prioritized interrupts (high priority PICU)
FFEC-FFED: IRQ6
FFEA-FFEB: IRQ5
FFE8-FFE9: IRQ4
FFE6-FFE7: IRQ3
FFE4-FFE5: IRQ2
FFE2-FFE3: IRQ1
FFE0-FFE1: IRQ0 --
FFDE-FFDF: IRQ15 -- 8 prioritized interrupts (low priority PICU)
FFDC-FFDD: IRQ14
FFDA-FFDB: IRQ13
FFD8-FFD9: IRQ12
FFD6-FFD7: IRQ11
FFD4-FFD5: IRQ10
FFD2-FFD3: IRQ9
FFD0-FFD1: IRQ8 --

The original IRQ interrupt is mapped to 8(16) prioritized interrupts by an Intel 8214 PICU per CPU (16 by cascading two PICUs with ETLG/ENLG, see Q133:jumper W1). In case of an IRQ interrupt vector fetch by the CPU: The PICUs provide the lower Bits of the new interrupt vector addresses (instead of the CPU's fixed FFF8-FFF9) IA1x,...,IA4x and IA5x=NOT(IA4x) (see Q209 74LS04 11B).
The P2 IRQ is split into 8 interrupts by one PICU (Q133, P2 IRQ0-7). The P1 IRQ is split by a Q133 PICU (low priority P1 IRQ8-15, XIRQ output) and a CMI-02 PICU (high priority P1 IRQ0-7, XIRQ PICU chain input) into 16 interrupts.
Note: an interrupt automatically switches to state A (system).
Note: Upon interrupt-vector fetch, IRQ+FIRQ are disabled via special Q209 hardware as required by OS9. The PICUs on the other hand ensure that no IRQ/FIRQ is lost (latched requests).


peripheral device interrupts:
CPU P1
0 ("IRQSYN"): ACINT (Q133, ACIA) || MIDINT (CMI-08, new CMI-28, MIDI)
1: TIMINT (CMI-02, master card timer)
2 ("P1IR1"): INTP1 (CMI-02, IPI)
3 ("P1IR10"): IPI1 (Q209, IPI) || SMIDINT (CMI-28, SMPTE/MIDI)
4 ("P1IR11"): AIC (CMI-07)
5: unused
6: unused
7: unused
8: CHINT2 (CMI-01-A, channel timer)
9: CHINT4 (CMI-01-A, channel timer)
10: CHINT6 (CMI-01-A, channel timer)
11: CHINT8 (CMI-01-A, channel timer)
12: CHINT1 (CMI-01-A, channel timer)
13: CHINT3 (CMI-01-A, channel timer)
14: CHINT5 (CMI-01-A, channel timer)
15: CHINT7 (CMI-01-A, channel timer)
CPU P2:
0: PERRINT (Q256, parity error) || RTCINT (Q133, RTC)
1: RINT (Q219)
2 ("P2IR2"): INTP2 (CMI-02, IPI)
3: IPI2 (Q209, IPI)
4: TOUCHINT (Q219)
5: PENINT (Q219)
6: ADINT (CMI-02, master card ADC) || IRQ8 (Q014)
7: DISK (QFC9, Q077)


DMA channels:
CPU P1:
1: P1DMAC (CMI-28)
2: unused
3: unused
4:
unused
CPU P2:
1: DMACLM (QFC9)
2: DMACLM (Q077)
3: unused
4:
unused

DMA priorities:
(chain ENL(level n) -> ETL(level n+1))
CPU P1:
0 (ENL source for 1): Q133 internal
1: RAM refresh on Q133 ("ENL1" to 2)
2: CMI-28
CPU P2:
0 (ENL source for 1): "EDL" (from QFC9, or from Q077 if no QFC9)
1: QFC9
2: Q077


DMA note: The DMA arbitration is implemented as a priority chain logic (ETL-ENL), distributed over the participating controller cards (and not as a centralized arbiter). Each CPU (Q209 P1/P2) has its independent DMA system with 4 channels each (see Q256 MMU). In order to avoid race-conditions with the DMA priority-chain logic, each controller latches its DMA request with the QASAR bus clock P202 (slight delays or differences are uncritical at this point) and asserts the DMA request line (for the required CPU). After a well defined delay (with respect to P202), which ensures that the DMA priority-chain logic has settled, the CPU asserts the acknowledge line, which in turn is used by the (now known) highest-priority controller to start its DMA and especially to activate its required DMA-channel line (4 per CPU). Lower-priority controllers must wait until the next clock phase for new DMA arbitration. Normally, the source of the DMA-priority chain (EDL) is the CPU clock divided by two, in order to have at least every second slot for its CPU. The QASAR bus is clocked by 2MHz, giving 1MHz per CPU and hence 500kHz for DMA per CPU. (Except the case where a Q777 SCSI card is installed, acting as the P2 DMA EDL source: If required, the Q777 increases the possible P2 bus usage by DMA to 2/3, hence giving 667kHz for higher throughput.)


Q219 graphics/light pen card (Type M):
Basically, the Q219 provides the functionality of the old graphics + light-pen system (Q045+Q025+Q148). However, the Q219 offers some additional/revised functions (and hence is not software-compatible with the old system). In contrast to the old graphics system, the Q219 now offers software-selectable access to the VRAM from both CPUs (P1 and P2), determined by a Q219 CPU-selection-Bit (see below) and the Q256 VENB-Bit.
A line contains 672 Bits (512 visible Bits=64 Bytes), with a total of 304 lines (256 visible lines). The horizontal direction is called y (!) and the vertical direction is x (!), with (0,0) in the upper left corner of the screen. Video output is in CCIR B/W format (625 lines, f_V=50Hz, f_H=15625Hz).
The on-board Bit-addressable video DRAM is organized as 8x16K Bits (similar to Q045+Q025). Access to the VRAM is synchronized with the 2MHz QASAR CPU clock (1 phase P1, 1 phase P2). Video readout to generate the video output signal is active for one clock phase, whereas the other phase is free for QASAR Bus access. Which phase, i.e. which CPU, has access is determined by a Bit from the 6821. This gives an alternating 1MHz 8-Bit readout and QASAR access. A FIFO and an 8-Bit shift register are employed to transform the 1MHz 8-Bit readout into a 10.38MHz pixel Bit-stream (i.e. 1.2975MHz 8-Bit) within the visible part of a line (note that 1.2975/672 < 1.0/512).
The VRAM can be directly accessed as a 16KByte region in the address range $8000-$BFFF (if VENB is active, see Q256).
The Q219 furthermore contains "vector acceleration" functions which are compatible with the Q045 (see Q045 in Series I/II section above).
The 8-Bit "scroll register" (6821) at $FCC4 is used as an x-offset (vertical!) in the readout cycle in order to implement a hardware acceleration of vertical text scrolling.
The Q219 card also contains a light-pen controller, used by the CMI Series IIx software (also OS9 device "/lpen"). The light-pen cursor is implemented via hardware (via video-output inversion). However, the light-pen is not used in the CMI Series III and MFX1/2 software (replaced by a graphics pad in the Alpha-keyboard or a mouse attached to an MFX-keyboard).

QASAR addresses:
8000-BFFF: VRAM direct access (if VENB active)
FCC0-FCC1: LPL1 (light pen horizontal position)
FCC2-FCC3: LPL2 (light pen vertical position)
FCC4-FCC7: PIA (vertical scroll latch, control Bits)
FCC8-FCCF: timer
FCD0-FCDB: graphics accelerator access ports
FE96: 'M' (MFX1/2 Q133 firmware: monochrome graphics card type)


VDU connector (monochrome video output from and light-pen input to Q219) pinout:
1: light-pen hit (input, inverted, TTL)
2: light-pen ground (signal return)
3: light-pen touch (input, inverted, TTL)
4: video ground (signal return)
5: video out (output, CCIR B/W)
For Q219 see above.
Note: This pinout is not compatible with Series III!


keyboard connector (on rear-panel) pinout:
1: +20V (output, power for Alpha keyboard only)
2: DON1 (output, enable data from keyboard)
3: -20V (output, power for Alpha keyboard only)
4: FLG1 (input, disable data from CMI)
5: DGND (signal return)
6: DIN (input, from music and Alpha keyboard)
7: GND (power return)
8: N.C.
9: KEYB DATA OUT (output, to music keyboard)
The Alpha-keyboard normally is connected to the music keyboard which, in turn, is connected to the CMI. The Alpha-keyboard can also be directly connected to the CMI.
Note: This pinout is not compatible with Series III!


SMPTE+MIDI general interface CMI-28 ("MP", "SMIDI"):
"old MP" <= Rev3 (in Series IIx)
"new MP" >= Rev4 (in Series III)
QASAR control port (old MP):
FCA0:
. Bit0: ~INT1
. Bit1: ~SMIDINT reset (set via INTC=private 0A0000)
. Bit2: SYNCSW
. Bit3: ~HALT
. Bit4: ~RESET
. Bit5: ~INT7
. Bit6: N/C
. Bit7:
N/C
QASAR control port
(new MP):
FCA0: (Bit addressable latch: D=Bit-data, BA=Bit-address)
. Bit0: BA2
. Bit1: BA1
. Bit2: BA0
. Bit3: BD
. Bit4: N/C
. Bit5: N/C
. Bit6: N/C
. Bit7: N/C
Bit latch address (new MP):
. 0: ~INT1
. 1: SMIDINT
. 2: MIDINT
. 3: SYNCSW (ext=0, int=1)
. 4: N/C
. 5: ~HALT
. 6: ~INT7
. 7: ~RESET

address space (CMI-28 CPU private):
000000-01FFFF: EPROMs (64KB used, "KMON")
040000-04FFFF: QASAR DMA P2 (Series III: wired to channel 4)
050000-05FFFF: QASAR DMA P1 (Series IIx, III: wired to channel 1)
060000-06001F: Timers
060020-06005F: MIDI ACIAs
060060-06007F: SMPTE
080000-09FFFF: private RAM (16-128KB)
0A0000: old MP only: SMIDINT to QASAR ("INTC")
0C0000: old MP only: CLOCK/RUN: Reset/Start ("SMP R/ST")
0E0000: old MP only: CLOCK/RUN: Run/Halt ("SMP R/H")
0E0000: new MP only: CLOCK/RUN: Reset/Start=Bit0, Run/Halt=Bit1 ("DMCNTRL")
standard load address: 080400

Interrupts (CMI-28 CPU private):
INT1: from QASAR (via FCA0 Bit)
INT2: Timer
INT3: MIDI ACIAs
INT4: SMPTE write
INT5: SMPTE read 0
INT6: SMPTE read 1
INT7 (NMI): from QASAR (via FCA0 Bit)


floppy controller QFC9:
WD1791 controller + FDC9229B PLL
QASAR control port:
FCE0-FCE1 (8" version)
FC70-FC71 ("Mini-Floppy" revision)
EPROM revisions:
DQFC910: for 8" drives (access selection via "HEAD LOAD")
DQFC911: for 3.5"/5.25" "Mini-Floppy" drives (access selection via "DS")


floppy and harddisk drives:
see software chapter



CMI Series III:


Overview:
Sound data is stored as 16-Bit linearly encoded sample words in a shared waveform RAM (WFM). The CMI Series III supports 16 channels of sample-playback, employing the variable-sample-rate concept for pitch variation. The CMI-35 digital cage backplane has an 8/16-Bit data/address bus (2MHz 2-slot synchronous) for the QASAR dual-6809 computer subsystem (Qxxx) and an additional 16/24-Bit data/address "WFM" bus (3.33MHz 8-slot synchronous) for the CMI waveform subsystem (CMI-xx). The 24-Bit WFM address refers to a full 16-Bit data word (with upper/lower Byte select lines), hence 16M 16-Bit words, i.e. max. 32MByte waveform RAM (older revisions used only 23 Bits, see "8-Bit mode" below; newer revisions use 25 Bits, providing 64MB address space, see MFX2 below). The 16-Bit waveform data bus is also present in a symmetrical form on the CMI-335 analog cage backplane (driven by the channel support card CMI-32) to transfer waveform data to the channel output modules (CMI-331, which contains the main DACs). Each channel card (CMI-31, one for two channels, each with an own control CPU) in the digital cage has a private connection to a corresponding channel output card (CMI-331, also one for two channels) in the analog cage. The sample input module (CMI-337 or CMI-346+347 or ESP-348+349, 2 channels) in the analog cage has a private connection to the waveform processor (CMI-33) or waveform supervisor (CMI-41) in the digital cage, which are responsible for waveform manipulation/loading/saving and sampling. The general interface processor (CMI-28) controls real-time events for the CMI-31s.
The CMI Series III channel cards were developed by Adrian S. Bruce.

Sample output principle:
Variable sample output rate for pitch variation (for each channel).
Each CMI-31 contains 24-Bit address generators and sample rate generators for its two channels, whereas the CMI-32 provides the 16-Bit data from the waveform RAM to the output CMI-331s and the master clocks. An 8-phase "round robin" scheme (clocked by the channel support card CMI-32) for the 8 CMI-31 cards is employed for deterministic access to the shared waveform RAM at fixed timeslots (at a rate higher than the highest desired sample output rate). Each CMI-31 toggles the channel for waveform RAM access from cycle to cycle (so the total number of channels available by this method is 16). The next waveform data word (16-Bit) is loaded into a first register stage on the CMI-331s by this round robin scheme: A sample rate generator pulse (asynchronous with respect to the round robin scheme) triggers the address generator logic to load the first register (within its next following timeslot) and to compute the next address within the following round robin cycle for the channel. Furthermore, this pulse loads its corresponding DAC register from the first register (which at this point of time contains the previous sample value loaded by the address generator due to the previous pulse). Since the fixed round robin rate (with channel repetition rate of 208kHz, see below) is higher than the max. sample output rate, the new waveform data in the first register stage is guaranteed to be already loaded before the next sample clock pulse arrives to load the DAC register from the first register. Note that one sample clock pulse consumes only one round robin timeslot on the bus (i.e. the bus is busier with higher pitch). Each time-slot used by a CMI-31 is signalled via a common WFM-bus strobe line ("time slot taken").
Unused time-slots are employed by the waveform processor/waveform supervisor (CMI-33/CMI-41) for WRAM refresh and waveform data read/write access.
Compared with a theoretical, perfect sample clock rate, data from the waveform RAM arrives in the first register stage with a jitter/resolution of 4.8microsec (208kHz see below). The following second register (DAC output) with a jitter/resolution of 58 nsec (17.15MHz see below) can be considered as a jitter filter.
The two-channel digital audio output function of the ESP-348 is realized by a serial connection to the CMI-41. Here, the CMI-41 reads the audio data directly from the waveform RAM at a fixed rate (at unsed time-slots, acting as an additional "channel card" without waveform post-processing).

Sample input principle:
The 2-channel sample input module (CMI-337 or CMI-346+347 or ESP-348+349) provides serial audio data (via current loops with optocouplers) directly to the waveform processor (CMI-33) or waveform supervisor (CMI-41), which in turn writes the 16-Bit words into the waveform RAM (at unsed time-slots). The CMI-41 employs its on-board 68450 DMA controller for the data transfer, whereas with the CMI-33 its 68000 is directly involved. (The CMI-41 on-board SCSI controller (NCR5380) also makes use of the CMI-41 DMA controller.)

Sample address generator principle
:
The address generators with loop capabilities for both channels are realized by a proprietary TTL state-machine with a 10MHz 24-phase micro-cycle clock (master oscillator of f_g=10MHz located on CMI-32) with various pulse-sequencer PROMs ("CLKG1", "CLKG2", "ADDGEN"). The round robin card switch rate is given by f_g/6 (approx. 3.33MHz, provided by CMI-32) which yields a card-repitition rate of f_g/(8*6) (approx. 416kHz, which also gives the 24 micro-cycles) and a channel repitition rate of f_g/(2*8*6) (approx. 208kHz). Note that the 24-Bit address remains constant until the next (asynchronous) sample rate generator pulse arrives which triggers the address generator. The waveform address incrementer kernel is implemented by an 8-Bit counter (Rev1: 2x74LS161, Rev2A: 2x74LS169) and an 8-Bit SRAM (2x2148HN-3) with various latches, registers, and glue logic. (Note: Micro-cycles have a fixed sequence with periodic pulses given by the PROMs. State-transistions of the glue-logic are hardwired. Hence, the design is not micro-coded, but should be considered as random-logic.) Each channel has two 24-Bit counters: one for the sample address, one for the loop end length detection. (Actually, each channel provides 2 independent loops with separate start address and length registers. At the end of the current loop, the new start address and length are read into the counter registers, with loop1/2 determined by the value of a selection Bit at that time. The end of a loop also generates an interrupt signal for the CMI-31's 68B09CPU. With Rev1, the address generator always starts with loading loop1 values. Start address, length and selection Bit values can be safely changed e.g. directly after entering the corresponding loop. With the CMI software, loop2 is employed as the "real loop". Loop1 is nothing but the region between the sample start and the "real loop"-end, and afterwards set to the block between the "real loop"-end and the sample-end.) Starting with CMI-31 Rev2A (May 1987), alternating looping (additional to the old forward looping) was possible. Micro-cycle PROM sequences were improved with PROM Rev2 (R2 for CMI-31 Rev1, R2A for CMI-31 Rev2A). Later revisions also provided a sample-coherent playback of the two CMI-31 channels (via shared sample clock, for use in Stereo mode, esp. MDR).

Sample rate generator principle
:
Each channel has its own frequency divider/multiplier, consisting of a 12-Bit BRM (bit-rate-multiplier, 2x7497, basically a binary counter with Bit-selection masks) followed by a variable "octave" divider by 2^N (1.5x74LS393). It triggers the DAC registers and the address generators. The master clock for all the BRMs is located on the CMI-32 and has a frequency of f_master=34.291712MHz/2. The BRMs provide a signal consisting of not evenly distributed pulses, but the following division stages act as "jitter filters" and produce an output signal that has only "small" phase fluctuations (i.e., a jitter of 1/f_master=58nsec) left. The output rate finally reads:
f_out=f_master*(M/4096)/(2^N) with M=1,...,4095 and N=5,...,12.
Default tuning/no modulation sample output rate:
C5 = 33488Hz (34.291712MHz/1024) (44.1kHz then corresponds to a shift of 4+196/256 semitones)
Pitch resolution:
worst case 1+1/2048 = 1/118 semitone (the CMI counts in pitch units (PU) of 1/256 semitones)
Sample output rate range (0PU corresponds to C5):
33Hz(-30720PU) ... 133kHz(+6143PU) (for Rev9.34, depending on rev.; note that the pitch resolution at sample output rates below 2093Hz(-12288PU) becomes worse than 1/118 semitones.)
The CMI-31 program ("ccprog") contains a pitch-table for a full octave, translating the pitch information (in pitch units) into a BRM factor (256*12=$C00 entries).
For analog sample input operation, the CMI-31 for CH1 is employed as the sample rate generator and CH1+2 as monitoring outputs (older revisions use CH3+4 for monitoring). In this case, the sample rate is limited to 5kHz-100kHz or 25kHz-50kHz, depending on the sample module and software.
During MDR operation, the variable sample-rate together with the loop-end interrupt capabilities can be employed to realize a sample playback rate which is synchronized to the master-SMPTE clock. (Compare ESP-348 digital audio output: fixed playback rate given by non-synchronized ESP-348 XTAL.)

Realtime control and envelopes
:
The general interface processor (CMI-28) is responsible for the real-time control of the CMI, it directly triggers the CMI-31 channel cards. The CMI-28 handles the MIDI and SMPTE interfaces and communicates with the QASAR sequencers (via timed MIDI frames) and MDR.
The dual-6809 QASAR has the overall control of the CMI system. CPU P2 runs the OS-9/6809 Level 2 operating system with the graphical user interface and the sequencers (RS, CAPS, TT, CL, PFTASK) as tasks. CPU P1 is used as a co-processor with its own operating system and tasks. The QASAR sequencers send/receive timed MIDI events to/from the CMI-28's play/record queues (contained within QASAR RAM). Here, the time-critical part is done by the CMI-28.
Each CMI-31 channel card has an on-board 68B09 CPU for control of the address/clock generators and the analog post-processing VCF/VCAs of its two channels. The VCF/VCAs together with the sample output DACs are located on the CMI-331 cards whereas the control voltages (level/cutoff/resonance) are generated by DACs on the CMI-31 boards. The CMI-31 68B09 is responsible for generating the real-time effects, where the program and control data (envelope+patch data, modulation function curves) is stored in the CMI-31's private 64KB RAM. Whenever a sample address generator reaches a loop end, the CMI-31 68B09 is informed by an IRQ interrupt. Communication with the QASAR computer subsystem is accomplished by DMA to the CMI-31's private RAM (with a channel card selection mask generated by the CMI-32, page address latch on the CMI-31) and bidirectional interrupts QASAR bus<->CMI-31 (especially a periodic 1msec "timer click" FIRQ generated by the CMI-32). Refresh of the CMI-31's private DRAM is synchronized with the QASAR refresh cycle. (Note: The CMI-31 68B09 CPU has no access to the QASAR data/address bus.)

8-Bit mode
:
Older revision waveform RAMs CMI-39 together with the CMI-33 waveform processor were also capable of an 8-Bit playback mode to address each individual Byte for 8-Bit sample data output (for direct playback of CMI Series II samples). These revisions had only 23-Bit addresses, where an additional 24th Bit (which later became address Bit 23 with the waveform supervisor CMI-41) was interpreted as the mode-switch 8/16 Bit. (Note that the CMI-31 always had a full 24-Bit address generator so there was no problem with this reinterpretation of the 24th Bit.) Due to the address space layout of the CMI-33, up to 14MB of waveform RAM can be used (although 23 Bits could address 8M words = 16MB). With the CMI-33, the WRAM is located in the upper 14MB of the 68000's 16MB space (i.e. the lowest 1M word WRAM space is not used). The CMI-41 however, can access 32MB of waveform RAM but does not provide the 8-Bit playback mode anymore (new WRAM revisions therefore required, see also MFX2 below). In 8-Bit playback mode, the WRAM interprets the 23 Bits as a Byte-address (i.e. max. 8MB. But since the lower 2MB are not used for WRAM, only 6MB accessible with the upper 8MB WRAM deactivated in 8-Bit playback mode.). With the CMI-39 in 8-Bit playback mode, the Byte is transmitted on the upper 8 Bits of the 16-Bit data bus with the lower 8 Bits forced to 0. This provides an effective 8-Bit sample playback on the 16-Bit CMI channel hardware. The 8-Bit playback is not to be confused with the Byte-addressing capabilities of the CMI-33/CMI-41 with LDS/UDS (lower/upper data strobes) on the 16-Bit waveform bus.

Comparison with Series IIx:

Basically, the main computer parts (dual-6809 QASAR with virtual memory support) of the Series IIx and the Series III are the same: Q209, Q133, Q256, QFC9, Q219, Q014, Q137; and even some CMI parts: CMI-28, CMI-07. The 16-Bit waveform processing with shared waveform memory (24-Bit sample word address address) is a new design (CMI-3x, CMI-3xx), compared to the 8-Bit sample resolution and the 16KByte channel-unique sample RAM of Series IIx machines. In Series III, two channels are processed by one CMI-31(digital part) + CMI-331(analog part), giving a total of 16 channels with 8 CMI-31 + CMI-331 boards, whereas the Series IIx provides 8 channels with 8 CMI-01-A boards. Sample input data is managed in the Series IIx by the CMI-02 plus CPU P1, and in the Series III by the CMI-33/CMI-41. All the real-time event management plus sound-generation control is done by the QASAR CPU P1 (with 8 extra interrupts from the channel cards) in Series I/II/IIx machines. With the Series III, however, the CMI-28 is the real-time event central, the channel cards (CMI-31) are self-sufficient with their own CPUs for sound-generation control, and QASAR CPU P1 is now used as a co-processor for CPU P2. In contrast to the IIx, Series III models are "only" samplers (i.e. comparable to the IIx Mode 4), lacking the Mode 1 synthesizer features (although the CMI-31 dual loop hardware has the potential. See Greg Holmes' infos for more on Series IIx modes). Nevertheless, the Series III provides a very powerful non-realtime additive synthesizer software (FFT, MIX, FLANGER, WE pages) using the waveform processor/waveform supervisor (CMI-33/CMI-41) and many realtime control features (e.g. control function curves). Furthermore, instead of the Series IIx QDOS, Series III machines run on a QASAR version of OS9/6809 Level 2.

Comments on Series III history:
(Note: this section is based upon the author's knowledge about the system and should be considered as a personal opinion!)
1983:
Originally, the Series III should have had an architecture analogous to the Series IIx, but with extended channel card capabilities. Each channel card processed one channel and contained its own 68B09 CPU with 64KB of private waveform RAM and 64KB of private program/data RAM. Playback from the WRAM was planned to be possible in 8-Bit and 16-Bit mode and with forward/backward looping capabilities, with the possibility to "chain" different channel cards to provide an extended sample playback length.
1984:
Further development suggested the usage of a shared waveform RAM with a separate WFM bus and an additional "powerful" 68000 waveform processor for sample data manipulation. This concept led to the "modern" Series III concept. Here, each CMI-31 channel card still contained a 68B09 but now responsible for 2 channels, where the 64KB private RAM was employed as program/data/control patch/function table memory. The shared waveform RAM is contained on separate cards. In these prototypes of Series III machines, the analog audio output section was not separated yet and was implemented as the CMI-36 output board with CMI-34 DAC/VCF/VCA board. Note that with the CMI-36 prototype, dynamic output routing was planned. The sample input module was the CMI-37. Such an early Series III system can be recognized by the "Series IIx"-like housing and was later available as the "Series IIIL" upgrade-kit for Series IIx machines: up to 8 channels (4xCMI-31) with up to 8MB of waveform RAM (4xCMI-39), channel support card (CMI-32), waveform processor (CMI-33), analog boards (CMI-36, CMI-34, CMI-37), SCSI controller+disk, backplane modification necessary.
1985:
The "final production" Series III offered space for 16 channels (8xCMI-31) with up to 14MB WRAM (7xCMI-39) and had a separate analog card cage (CMI-335 backplane) with the CMI-337 sample input and eight 2-channel outputs (8xCMI-331). Dynamic routing was later introduced with the ESP-RT1 16-to-24-output dynamic router module.
Note: The shared-WRAM concept used in Series III machines somehow resembles the QASAR M8 WRAM design (the QASAR-bus + dual-CPU being replaced by the WFM-bus + waveform processor). Nevertheless, the CMI-31's dual-loop capabilities aren't fully exploited for synthesizer purposes. These two loops probably could have been used to implement a "Series III wavetable synthesizer" analogous to the old CMI "Mode 1".


mainframe digital boards:

CMI-39 2MB waveform RAM (16-Bit/24-Bit data/address, must be revised for use with CMI-41)
CMI-40 4MB waveform RAM (16-Bit/24-Bit data/address)
CMI-43D 8MB waveform RAM (16-Bit/24-Bit data/address), D=dual-inline DRAM chips
WFM32 32MB waveform RAM (16-Bit/24-Bit data/address) distributed by Horizontal Productions (replaces all CMI-xx waveform memory boards, info)
CMI-31 2 channel card ("CC", 24-Bit address generators, 4x7497 + 3x74LS393 sample clock generators, private connection to corresponding CMI-331, 68B09 @2MHz, 64KB private RAM, 1xAD7226KN quad 8-Bit CV-DAC for VCF on CMI-331, 2xAD7548JN 12-Bit CV-DAC for VCA on CMI-331, MC3487P symmetrical line driver for strobe pulses to CMI-331, later revisions offer sample-coherent stereo playback, Rev2A with alternating looping, special revisions necessary for use with CMI-41)
CMI-32 channel support card (68B21P channel mask PIA, 68B40P timer, 20.0000MHz WRAM Bus and 34.2917MHz sample clock master oscillators, 5xMC3487P symmetrical line driver for 16-Bit bus on CMI-335 and master clock signals on CMI-35, channel timing signals)
CMI-33 waveform processor ("WP", 14MB waveform address space, 8/16-Bit mode, private bidirectional serial connection to sample module, 68000 @10MHz, 512KB private 16-Bit RAM)
CMI-41 waveform supervisor ("WS", replaces CMI-33, 64MB waveform address space (WRAM in lower 32MB), private bidirectional serial connection to sample module, 68020RC12 @10MHz CPU, 68881RC16 @16MHz FPU, 68450RC10 @10MHz DMA controller, 1/4MB private 32-Bit DRAM, on-board NCR 5380 SCSI controller "WS SCSI", CMI-35 + CMI-31s + WRAM must be revised for use with CMI-41)
CMI-28 see Series IIx
CMI-07 see Series IIx
Q256 see Series IIx
Q356 System RAM with paging hardware (1MB) = 4xQ256
Q014 see Series IIx (OS9 driver "acia")
Q133 see Series IIx (OS9 driver "sacia")
Q209 see Series IIx
Q219 see Series IIx
QFC9 see Series IIx

QFC9
"Mini-Floppy"

revised QFC9, 5.25"/3.5" floppy controller for MFX1, MFX2 (for PC-style floppy drives, OS9 devices: 77-track /m0 and /m1, 80-track /mh0 and /mh1)
Q777 SCSI controller (proprietary, QASAR bus)
Q007 P2 DMA chain ENL source (EDL) if Q777 not present (and QFC9 not used as source or not present)
ESP-TS1 TurboSCSI controller for MFX2 (see below)
ESP-96K Waveform accelerator for MFX2 (see below)

CMI-35 digital mainboard
CMI-311 WFM bus terminator (on CMI-35 at slot 1)
CMI-312 QASAR bus terminator (on CMI-35 at slot 8)
CMI-313 QASAR bus terminator (on CMI-35 at slot 16)
CMI-317 connector board, control LEDs (back side) CMI version
CMI-318 mains voltage selector board
CMI-353 SCSI terminator (external)
CMI-354 connector board, control LEDs (back side, attached to CMI-355) MFX revision
CMI-355 interface board (back side, replaces CMI-317) MFX revision
Q137 see Series IIx
SMPSU switching mode digital power supply
CMI-314 power regulator in Alpha-keyboard (ANK)

mainframe analog boards:
CMI-332 MIDI and clock I/O (to CMI-28, MIDI port D input -> keyboard connector on CMI-317/CMI-355)
CMI-333 SMPTE+Sync+Metronome I/O (to CMI-28)
CMI-334 audio mixer output

ESP-RT1

24 output router/mixer (arbitrary dynamic mapping/mixing of the 16 channel outputs to 24 extra outputs, controlled via 16-Bit PIA signals from Q133, ESP-RT1A("ESP-337"): main router/mixer board, ESP-RT1B de-balancing card, 16x3x74HC4351 1:8 latching analog MUX, 12xLM837N sym. output driver, via optional resistor network: phones output of Out1 (Left)/Out2 (Middle)/Out3 (Right))

ESP-RT1B

16 channel de-balancing card, 1x on ESP-RT1
CMI-331 2 channel output (private connection to corresponding CMI-31, 5xMC3486P symmetrical line receivers for 16-Bit bus on CMI-335 and strobe pulses from CMI-31, 8x74LS273 registers for DACs, 2xMP7616JN 16-Bit DAC, 2xCMI-338 (for TOKO PALH 1107E) 22kHz LP filters, 10x dbx2150A VCAs (5 per channel: 1 as VCA, 4 in proprietary VCF circuit with capacitors + opamps), amplitude/cutoff freq./resonance CVs from CMI-31, audio outputs also to CMI-335 backplane for mixer/router, older revisions (with CMI-334) had channel mix select line with CD4053)
CMI-338 22kHz LP filter module (for TOKO PALH 1107E), 2x on CMI-331 (3xLF353N)
CMI-337 2 channel analog sample input (private bidirectional serial connection to CMI-33/CMI-41, -10dBm input level, ADC-clock from channel card 1/2, 5-49.5kHz mono/stereo and 5-100kHz unfiltered mono)
CMI-346+347 2 channel digital+analog sample input (private bidirectional serial connection to CMI-33/CMI-41, CMI-347: analog input option board: Apogee filter+ADC? (switchable bypass), -10/+4dBm input level, ANALOG: 5-96kHz mono/stereo/unfiltered mono, XTAL: 44.1/48kHz analog, DIGITAL: 30-50kHz AES/EBU)
ESP-348+349 2 channel digital+analog sample input and digital output, sample rate conversion ("XDR" sample module, private bidirectional serial connection to CMI-41, ESP-349: analog input and PLL board, AK5326-VP stereo 16-Bit ADC with 64-times oversampling (@32/44.1/48kHz, on ESP-349), 2xAD7524JN 8-Bit MDAC (on ESP-349) for level control (switchable bypass), -10/+4dBm input level, ANALOG: 25-50kHz mono/stereo (ADC @32/44.1/48kHz), XTAL: 32/44.1/48kHz analog, DIGITAL: 32/44.1/48kHz AES/EBU, sample rate conversion, Motorola XSP56001ZL20 @20MHz 24-Bit DSP with 3x8KB CY7C185-20 private SRAM, Sony CX23033 + CX23053 + DS8921 AES/EBU transmitter + receiver, RS232 serial port)

CMI-335 analog mainboard
CMI-336 shield PCB for analog boards
CMI-310 analog and keyboard power supply, phones out (mixed audio from CMI-334 or ESP-RT1, metronome click from CMI-28 via CMI-333)


old prototype boards (Series IIIL):

CMI-36 output board (esp. dynamic audio router)
CMI-34 8-channel audio board (attached to CMI-36)
CMI-37 analog sample input board (private serial connection to CMI-33)

music keyboard (MKB):
CMI-10 see Series IIx (with Series III MIDI firmware and MIDI out)
CMI-11 see Series IIx
CMI-12 see Series IIx
CMI-14 see Series IIx
CMI-319 analog controller board


digital card cage
(front side):
backplane = CMI-35
1: CMI-39, CMI-40, CMI-43D, ESP-96K
2: CMI-39, CMI-40, CMI-43D
3: CMI-39, CMI-40, CMI-43D
4: CMI-39, CMI-40, CMI-43D
5: CMI-39, CMI-40, CMI-43D
6: CMI-39, CMI-40, CMI-43D
7: CMI-39, CMI-40, CMI-43D
8: CMI-31 (channel 15/16)
9: CMI-31 (channel 13/14)
10: CMI-31 (channel 11/12)
11: CMI-31 (channel 9/10)
12: CMI-31 (channel 7/8)
13: CMI-31 (channel 5/6)
14: CMI-31 (channel 3/4)
15: CMI-31 (channel 1/2)
16: CMI-32, ESP-TS1
17: CMI-33, CMI-41
18: CMI-28
19: CMI-07
20: Q256 (card 1)
21: Q256 (card 0), Q356
22: Q014
23: Q133
24: Q209
25: Q219
26: QFC9
27: Q777, Q007

analog card cage (back side):
backplane = CMI-335
1: -
2: CMI-332
3: CMI-333
4: CMI-334, ESP-RT1
5: CMI-334, ESP-RT1
6: CMI-331 (channel 15/16)
7: CMI-331 (channel 13/14)
8: CMI-331 (channel 11/12)
9: CMI-331 (channel 9/10)
10: CMI-331 (channel 7/8)
11: CMI-331 (channel 5/6)
12: CMI-331 (channel 3/4)
13: CMI-331 (channel 1/2)
14: CMI-337, CMI-346+347, ESP-348+349


peripheral device address map:
see Series IIx



interrupt vectors:
see Series IIx
Note: The CMI Series III has only one PICU per 6809 CPU (on Q133). Hence, 8 interrupt levels per CPU.


peripheral device interrupts:
CPU P1
0: MIDINT (CMI-28, MIDI)
1: TIMINT (CMI-32, channel support card timer)
2: CHINT1 (CMI-31, all channel cards)
3: IPI1 (Q209) || SMIDINT (CMI-28, SMPTE/MIDI)
4: AIC (CMI-07)
5: unused
6: unused
7: unused
CPU P2:
0: PERRINT (Q256, parity error) || RTCINT (Q133, RTC)
1: RINT (Q219)
2: unused
3: IPI2 (Q209)
4: TOUCHINT (Q219)
5: PENINT (Q219)
6: ACINT (Q133, ACIA) || IRQ8 (Q014)
7: IRQD (QFC9, Q777)


DMA channels:
CPU P1:
1: P1DMAC (CMI-28)
2: P1DMAC (CMI-33, CMI-41)
3: unused
4: unused
CPU P2:
1: DMACLM (QFC9)
2: DMACLM (Q777)
3: P2DMAC (CMI-33, CMI-41)
4: P2DMAC (CMI-28)

DMA priorities:
(chain ENL(level n) -> ETL(level n+1))
CPU P1:
0 (ENL source for 1): "ENL1" (RAM refresh on Q133)
1: CMI-28 (WS revision: CMI-41)
2: CMI-33 (WS revision: CMI-28)
CPU P2:
0 (ENL source for 1): "EDL" (from Q777, or from QFC9 if no Q777)
1: QFC9 (if no QFC9: bridge on Q777: EDL to ETL of CMI-28)
2: CMI-28
3: CMI-33 (WS revision: CMI-41)
4: Q777

Note: See CMI Series IIx above! The Q007 card must be installed as the P2 DMA chain ENL source (EDL) if the Q777 is not present and the QFC9 is not used for EDL (or not present).


SCSI controller Q777:
QASAR control port:
FCE2-FCE3

The Q777 is intended for usage with a WP (CMI-33) system (i.e. software Rev<=6). As a QASAR bus peripheral, it can only transfer data to/from the QASAR memory. The Q777 has its own on-board DMA counter and address generator.
The QASAR low-level driver is contained within an on-board ROM, transferred into QASAR RAM during system startup (see below).
For CMI sample-saving/loading or harddisk-recorder operation ("DTM", see software chapter below), the WP is involved as a mediator between the QASAR memory and waveform memory.

If a Q777 SCSI card is installed, it also provides the P2 DMA EDL source, replacing the QFC9 EDL signal (via bridges on the controller boards). In contrast to the QFC9 EDL, which provides a maximum P2 bus usage by DMA of 1/2 (i.e. 500kHz), the Q777 optionally increases this value to 2/3 (hence giving 667kHz) for higher throughput (see DMA chapter above for more information). Note that the Q777 has the lowest P2 DMA priority, though.


Waveform Bus:

CMI-33 (WP) system:

Waveform-Bus Byte-addresses (see WP section for WP address mapping):
000000-1FFFFF: not used (not accessible by WP!)
200000-FFFFFF: 14MB WRAM space
Note: With the CMI-39, the waveform Bus has 23 address lines and one "not-8-Bit" mode line. In 8-Bit mode, the address lines refer to Byte-address A0-A22 with A23 assumed 0 (see also "8-Bit mode" section above). In 16-Bit mode, the address lines refer to Byte-address A1-A23 with LDS/UDS lines selecting the Bytes on the 16-Bit waveform data Bus. Due to the WP's address space layout (see 8-Bit mode chapter above), the lowest 2MB waveform bus range cannot be employed, providing a maximum of 14MB WRAM (lower 6MB usable for 8-Bit mode) with 7x CMI-39.
Note: The CMI-40 (with jumper to W1=WP) could be used with the WP. Here, however, the 8-Bit mode is no longer supported. Instead, the "not-8-Bit" mode line is used as a "14MB bank select" line. Again, due to the WP's address space layout (see 8-Bit mode chapter above), the lowest 2MB waveform bus range cannot be employed. As a special case, the CMI-40 which is selected for the lowest 4MB region in the upper 14MB block, uses its lower 2MB for the bank 1 addresses 2MB-4MB and its upper 2MB for bank 2 addresses 2MB-4MB. Hence, providing max. 28MB WRAM for the WP with 7x CMI-40 cards.
WRAM cards: CMI-39, CMI-40 (with jumper W1=WP)

CMI-41 (WS) system:
Waveform-Bus Byte-addresses (add 02000000 for WS address!):
00000000-01FFFFFF: 32MB WRAM space (accessible by CMI-31)
02000000-03FFFFFF: 32MB for WS-peripherals+WRAM (not accessible by CMI-31!)
Note: The 23 waveform Bus address lines are interpreted as Byte-address A1-A23 (similar to former WP 16-Bit mode). The former "not-8-Bit" line becomes Byte-address A24. In MFX2, "Not-address-strobe " line (~WAS) is interpreted as Byte-address A25. The LDS/UDS lines select the Bytes on the 16-Bit waveform data Bus.
WRAM cards: CMI-43D, CMI-40 (with jumper W1=WS), revised CMI-39 (not recommended)


Waveform RAM (CMI-39/CMI-40/CMI-43D):

Each waveform RAM board (max. 7, in slots 1-7) has DIP switches to set its base address.
4 switches (left to right, logical 1 means ON (up), 0 means OFF (down)):
CMI-39 2MB: abcd => base=2MB*(not(a)*8+not(b)*4+not(c)*2+not(d))
CMI-40 4MB: 1abc => base=4MB*(not(a)*4+not(b)*2+not(c))
CMI-43D 8MB: 11ab => base=8MB*(a*2+b)


channel support card/channel cards (CMI-32, CMI-31) (PENB active):
QASAR address space:
E000-E1FF:
. E0x0-E0xF: channel card x control (x=0,...,7)
. E080-E08F: channel card control (depending on PIA mask)
. E090-E093: support card channel mask PIA (2x8-Bit for P1/P2 access)
. E098-E09F: support card timer
. E100-E1FF: channel card DRAM DMA window (8-Bit page given by latches on CMI-31, depending on PIA mask)
channel card control offsets (E00x-E08x):
. 0: STATUS (read Bit 6&7, reset CHINT)
. 2: CNTRL (write Bit7: RESET)
. 4: UP2 (P2 page latch)
. 6: UP1 (P1 page latch)
. 8: N.C.
. A: ATT (write: set IRQ)
. C: N.C.
. E: N.C.

channel card address space (CMI-31 CPU private):
0000-FE7F: private DRAM
FE80-FEFF: peripherals:
. FE80-FE83: VCF DACs (2x2x8-Bit)
. FE84-FE8B: VCA DACs (2x12-Bit)
. FE8C: VCA DACs load
. FE8E: address generator control, VCA CV filter control
. FE90-FE93: clock generator control
. FE94: reset FIRQ
. FE95: loop direction control in Rev2 (unused in Rev1)
. FE96: set CHINT to QASAR
. FE97: read IRQ status
. FEC0-FEFF: address generator SRAM
FF00-FFFF: private DRAM (especially interrupt vectors)

channel card waveform address generator space (24 Bits)
:

CMI-33 (WP) system:
(Note: WRAM Byte-address space 000000-1FFFFF not used! see WP)

with CMI-39:
upper generator Bit is "not-8-Bit" mode line
generator 200000-7FFFFF
= WRAM Byte-address 200000-7FFFFF 8-Bit mode (max. 6MB)
generator 900000-FFFFFF
= WRAM Byte-address 200000-FFFFFF 16-Bit mode (max. 14MB)

with CMI-40: upper generator Bit is "bank select" line, always 16-Bit mode
generator 100000-7FFFFF
= WRAM Byte-address 200000-FFFFFF bank 1 (max. 14MB)
generator 900000-FFFFFF
= WRAM Byte-address 200000-FFFFFF bank 2 (max. 14MB)

CMI-41 (WS) system:

(Note: add 02000000 for WS address!)
always 16-Bit mode
generator 000000-FFFFFF
= WRAM Byte-address 00000000-01FFFFFF (max. 32MB)
(Note: waveform Bus Byte-address 02000000-03FFFFFF not accessible by channel card!)

CMI-31 LEDs:
from top to bottom:
1: CH1 running
2: CH2 running
3: CPU running (non-RESET)
4: FIRQ idle (non-FIRQ)


general interface CMI-28 ("MP", "SMIDI"):
see Series IIx


waveform processor CMI-33 ("WP"):
QASAR control port:
FC5C:
. Bit0: ~IPL0
. Bit1: ~IPL1
. Bit2: ~IPL2
. Bit3: ~HALT
. Bit4: ~RESET
. Bit5: ~8BIT
. Bit6: N/C
. Bit7:
N/C

address space (CMI-33 CPU private):
000000-01FFFF: EPROMs (64KB used, "KMON")
040000-04FFFF: QASAR DMA P2 (wired to channel 3)
050000-05FFFF: QASAR DMA P1 (wired to channel 2)
060000-07FFFF: sample module I/O
080000-0FFFFF: private RAM (512KB)
200000-FFFFFF: waveform RAM (see below)
standard load address: 080400

with CMI-39:
"WP 8-Bit mode"=0
:
200000-FFFFFF
= WRAM Byte-address 200000-FFFFFF 16-Bit mode (14MB)
"WP 8-Bit mode"=1:
400000-FFFFFF
= WRAM Byte-address 200000-7FFFFF 8-Bit mode (6MB)

with CMI-40: always 16-Bit mode
"WP 8-Bit mode"=0
:
200000-FFFFFF
= WRAM Byte-address 200000-FFFFFF bank 2 (14MB)
"WP 8-Bit mode"=1:
200000-FFFFFF
= WRAM Byte-address 200000-2FFFFF bank 1 (14MB)

Interrupts (CMI-33 CPU private):
IPL0-IPL2 (=>INT1-INT7): directly via QASAR FC5C Bits


waveform supervisor CMI-41 ("WS"):
QASAR control port:
FC5C: (Bit addressable latch: BD=Bit-data, BA=Bit-address)
. Bit0: BD
. Bit1: BA0
. Bit2: BA1
. Bit3: BA2
. Bit4: N/C
. Bit5: N/C
. Bit6: N/C
. Bit7: N/C
Bit latch address:
. 0: ~INT1
. 1: ~INT3
. 2: ~INT5
. 3: ~INT7
. 4: ~CDIS (68020 cache disable)
. 5: ~WS SCSI
. 6: ~HALT
. 7: ~RESET
FDE0 (KMON20/jscsi mailbox: "wsmem", "wsc__", "wc___", "wk___")

address space (CMI-41 CPU private):
00000000-007FFFFF: mapped to EPROM (on RESET) or private RAM
00820000-0082FFFF: QASAR DMA P1 (wired to channel 2)
00860000-0086FFFF: QASAR DMA P2 (wired to channel 3)
01000000-0100FFFF: system control

01010000-0101FFFF: ADC (sample module I/O)
01200000-013FFFFF: WS SCSI controller
01400000-015FFFFF: WS DMA controller
01600000-017FFFFF: EPROM (32-64KB used, "KMON20")
01800000-01FFFFFF: private RAM (1-4MB used)
02000000-05FFFFFF: waveform bus (64MB, old revision: 32MB)

= waveform Bus Byte-address 00000000-03FFFFFF
.02000000-03FFFFFF: WRAM (max. 32MB)
. = waveform Bus Byte-address 00000000-01FFFFFF
.04000000-05FFFFFF: waveform accelerator, TurboSCSI, ...
. = waveform Bus Byte-address 02000000-03FFFFFF
system control (01000000):
. Bit0: WS SCSI
. Bit1: WS SCSI
. Bit2: ADC BIT17 output
. Bit3: N/C
. Bit4: ADC
. Bit5: ADC
. Bit6: WS SCSI interrupt enable
. Bit7: WS INT interrupt enable (in older Rev: ADC interrupt enable)
standard load address: set via KMON20

Interrupts
(CMI-41 CPU private):
INT1: from QASAR (via FC5C latch Bit) ("system tick", typ. 16Hz)
INT2: WS SCSI
INT3: from QASAR (via FC5C latch Bit) ("IPI")
INT4: WS DMA (issues user-defined vectors)
INT5: from QASAR (via FC5C latch Bit) ("CCINT")
INT6: WS INT (TSCSI, DSP96K) (in older Rev: ADC)
INT7: from QASAR (via FC5C latch Bit)

WS DMA channels
(CMI-41 private)
channel 0: ADC
channel 1: ADC
channel 2: WS SCSI driver
channel 3: TSCSI driver (TSCSI WRAM to/from WS PRAM and QASAR)
WS DMA user-defined vectors: (at INT4)
vector 0: WS SCSI driver
vector 1: WS SCSI driver
vector 6: TSCSI driver
vector 7: TSCSI driver

PALs/GALs:

IOPAL, ASPAL: WS private address decoding
DRPAL, BYPAL: WS private DRAM control, data size control
C1PAL, C2PAL, CLPAL: QASAR bus interface control
WBPAL (later WXGAL): waveform bus interface control
SMPAL, SCPAL: WS SCSI control
ADPAL: sample module (ADC) interface control

CMI-41 LEDs:
form top to bottom:
1: RESET
2: HALT
3: WS SCSI
4: CDIS (68020 cache disable)


XDR sample/digital I/O module (ESP-348+349, "DSP sampler"):
The sample input/digital output module ESP-348 is connected to the CMI-41 via a bidirectional serial interface with a fixed Bit-rate of 64*32kHz. Transmissions to/from the ESP-348 consist of 17-Bit data packets ("frame", in contrast to 16-Bit frames used with the CMI-337), which contain audio data or control information. The ESP-348 provides the Bit-clock and frame-trigger signals to the CMI-41. All serial data transmissions form the CMI-41 to the ESP-348 and vice versa are locked to this clock. The actual frame-rate is determined by the ESP-348, depending on the desired sample-data transfer-rate to the CMI-41. Given the 64*32kHz Bit-rate, the theoretical limit therefore is a 60kHz Stereo sample-rate. For Mono, every second frame is omitted, hence providing also max. 60kHz in that case (in contrast to the CMI-337, which offers an unfiltered Mono-mode with up to 100kHz). The CMI-41 furthermore provides a sample-frame-clock reference signal to the ESP-348, stemming from the CH1 CMI-31. Hence, we have 3 signals ESP-348 -> CMI-41 and 2 signals CMI-41 -> ESP-348, all transmitted via current loops with opto-couplers.
A 56001 DSP on the ESP-348 is employed to route/convert/scale sample-input data and digital output data. Sample-rate conversion could be necessary for harddisk-recording (MDR) using the digital AES/EBU input if there are slight source frame-rate deviations/fluctuations (with respect to the CMI-31 clock which is synchronized to the SMPTE master clock with MDR) to guarantee exact track time-scales during playback with fixed sample-rate (note that the data-rate to the WRAM/disk during record/sampling is given by the DSP output-rate, see below).
The analog input ADC circuits and the AES/EBU input PLL are contained on the ESP-349 board, which is directly connected to the ESP-348 board.
DSP Inputs+Outputs:
The 56001 DSP on the ESP-348 uses its SSI serial I/O interface for audio I/O and communication with the CMI-41.
The ESP-348 has 4 master clock sources: three XTAL clocks (256*32/44.1/48kHz) and the AES/EBU input clock (256*input DIGITAL IN frame-rate). All further clocks are derived from these masters. Note that the AES/EBU input master clock is generated by a PLL circuit on the ESP-349 (directly synchronized to the AES/EBU input biphase-mark-code).
The CMI-31 frame-clock is only used as sample-rate conversion reference for ESP-348 to CMI-41 data transfer (DSP output frame clock) if sample rate conversion is activated.
Due to the interface design, the frame- and Bit-rate from the CMI-41 to the ESP-348 are identical with the rates from the DSP output to the CMI-41 and the AES/EBU transmitter.
DSP Inputs:
The serial data input (pin SRD) is obtained from a multiplexer: The CMI-41 data (control-data or sample data from MDR for digital audio output), the AES/EBU DIGITAL IN data (from the CX23053 on the ESP-348), or the ANALOG IN data from the ADC on the ESP-349. Each data source also has a separate Bit- and frame-clock, multiplexed in parallel with the data. (DSP receive clock = pin SC0, receive frame sync = pin SC1. The input frame-clock also generates IRQB.) Note that data from the CMI-41 has highest priority (and generates IRQA in order to notify the DSP asynchronously), selected by "BIT17" (=D16 in the frame).
DSP Outputs:
The ESP-348 DSP provides a serial data output (pin STD) to the AES/EBU DIGITAL OUT (via CX23033 on the ESP-348, mutable via gate) and the CMI-41 in parallel. The DSP output frame-rate f_out (transmit frame sync = pin SC2, SSI transmitter interrupt employed) is multiplexed from the following 5 sources: AES/EBU DIGITAL IN, selectable Quartz clock f_XTAL (XTAL: 32/44.1/48kHz), or PLL/VCO stabilized CMI-31 clock f_CH (via the CMI-41, see above). However, the DSP output Bit-rate (transmit clock = pin SCK) is given by a fixed clock of 64*32kHz (independent of the variable output frame-rate). Note that during sampling, the data-rate with which audio words are written to the WRAM (by help of the CMI-41) is given by the DSP output frame-rate (f_out, and not f_CH, see monitoring artefacts below).
With SMP RATE CONV=NO, the 56001 DSP output frame rate f_out is identical to its input frame rate (f_out=f_in), and input sample data is simply passed through to the CMI-41 (and DIGITAL OUT, if it is not deactivated via a special gate).
With SMP RATE CONV=YES, the DSP generates sample data words (by sin(x)/x interpolation) at the given CH1 CMI-31 sample-rate f_CH, hence providing a sample-rate conversion from the DSP input source frame-rate f_in to the DSP output frame-rate f_out (here f_out=f_CH). For the phase detection (input to output frame), a 4-Bit counter (continuously running at the master clock of 256*f_in and sampled at the DSP output frame-rate) is employed. From this information, the DSP is able to convert the frame-rates with a phase-resolution of 1/256 within a frequency window of approx. +/-3%. (The Rev6 ESP-348 firmware additionally offers an automatic sample-rate conversion between 44.1k and 48k and digital scaling for DIGITAL IN under Rev11 MDR operation.)
Analog input:
The ADC on the ESP-349 (AK5326-VP, capable of 24-50kHz Stereo sample-rates, 64-times oversampling, 3-stage digital filter) always runs at a (low jitter) 32/44.1/48kHz sample data rate (derived from the master clocks), depending on the chosen SAMPLE RATE:
25000-37999: 32k
38000-44999: 44.1k
45000-50000: 48k
(With ANALOG/XTAL and SMP RATE CONV=NO, the ESP-348 provides only these three sample data rates to the CMI-41, ignoring the CMI-31 rate. For the ESP-348/349, ANALOG mode with 32000/44100/48000 is equivalent to the XTAL 32k/44.1k/48k mode).
On the ESP-349, two multiplying DACs (AD7524JN) are employed as an input level attenuator (0-100%) with a relay-switched main level selector (-10/+4dBm). The additional attenuator control bypass switch (ATTENUATOR IN/OUT relay) is replaced by an AES/EBU PLL deactivation circuit in newer revisions.
Digital audio input:
The AES/EBU receiver (CX23053) is synchronized to the AES/EBU input master clock. Here, the ESP-349 board contains a PLL circuit to generate the master clock (256*frame-rate) for the CX23053 (instead of the CX23053's built-in PLL) from the AES/EBU input Bit-stream (biphase-mark-code signal). (The "LOCK" LED is driven by the input receiver CX23053). The CX23053 receiver provides his Bit-clock, serial audio data, and frame-clock to the DSP input multiplexer (see above). (For additional Rev6 firmware features see the "DSP outputs" section above.)
Digital audio output:
In this mode (supported by MDR Rev9 and later), the CMI-41 serial output to the ESP-348 is used for digital audio output (the CMI-41 acting as a "channel card", but without any post-processing). The DSP obtains its input audio-data directly from the CMI-41. The CX23033 AES/EBU transmitter obtains his data from the DSP output, its Bit-clock input is connected to 64*32kHz DSP output Bit-clock (fed to DSP pin SCK), and its frame-clock input is connected to the selected DSP output frame-clock (fed to DSP pin SC2). (Note that the variable AES/EBU transmitter output Bit-rate has nothing to do with the 64*32kHz Bit-clock for the transmitter serial data input from the DSP output.) The CX23033 output master-clock (128*frame-rate for the biphase-mark-code) is derived from the selected ESP-348 master clock. A special gate is used to switch the digital audio data signal from the DSP to the AES/EBU transmitter (which is muted during sample operation and can be activated by MDR).
Note that the frame- and Bit-clocks for the data transfer from the CMI-41 to the ESP-348 are identical with the DSP output clocks, which exactly are also used for the AES/EBU output. During digital-output operation, the data-rate with which audio words are read from the WRAM (by help of the CMI-41) is given by the CMI-41 output rate. Hence, sample-rate conversion for digital-output operation is impossible. Furthermore, since the CMI-31 frame-clock is uncorrelated to the XTAL-generated output master-clock (on the ESP-348) for the AES/EBU transmitter, only the three XTAL sources on the ESP-348 can be employed as frame-clocks for digital-output operation. Hence, the harddisk-recorder cannot guarantee exact track time-scales for a track played back on the digital audio output, because the XTAL crystal oscillators are not synchronized to the master-SMPTE clock (in contrast to the analog outputs via CMI-31, see chapter above).
Auxilliary debug interfaces:
The ESP-348 also provides an RS232 I/O (PORT#1), which is connected to the SCI serial I/O interface of the DSP (pins RXD and TXD; SCLK not used). PORT#2 provides a manual DSP reset input (to PBRST of the reset / watchdog DS1232) and a buffered 1-Bit output line from the DSP.
Sampling:
In sample mode, the CH1/2 CMI-31 is employed as a frame-rate source f_CH (if SMP RATE CONV=YES) and for monitoring. Note that during sampling, the data-rate with which audio words are written to the WRAM (by help of the CMI-41) is given by the DSP output frame-rate f_out (which is !=f_CH in general if SMP RATE CONV=NO).
During monitoring, a small waveform RAM block (Rev9: 0x100, Rev11: 0x800) is used for cyclic buffering of sample input data (at f_out frame-rate) and readout via CH1/2 CMI-31 (at f_CH frame-rate; if both rates are different, monitoring pitch-artefacts are audible, i.e. SMP RATE CONV=NO and f_out!=f_CH).

address spaces (56001 private):
Program memory space:
0000-001F: DSP on-chip bootstrap ROM (read-only at RESET)
0000-01FF: DSP on-chip program RAM (write-only at RESET)
0000-01FF: DSP on-chip program RAM (r/w after RESET)
0200-FFFF: external port A
X data memory space:
0000-00FF: DSP on-chip X data RAM
0100-01FF: DSP on-chip X data ROM
0200-FFBF: external port A
FFC0-FFFF: DSP on-chip I/O peripherals
Y data memory space:
0000-00FF: DSP on-chip Y data RAM
0100-01FF: DSP on-chip Y data ROM
0200-FFFF: external port A
external port A:
0000-1FFF: ESP-348 SRAM
8000-FFFF: program space: ESP-348 EPROM
FFFF: data space, read: ESP-348/ESP-348 status Bits and sample phase det.
FFFF: data space, write: ESP-349 attenuator
external port B:
ESP-348/ESP-349 control and status Bits
external port C:
SSI (audio and WS I/O) and SCI (debug RS232 port)


VDU connector (monochrome video output from Q219) pinout:
1: 16VAC (output, power for monitor)
2: 16VAC (output, power return for monitor)
3: N.C.
4: video out (output, CCIR B/W)
5: video ground (signal return)
For Q219 see Series IIx above.
For color graphics see CG1/CG2/CG3 below.
Note: This pinout is not compatible with Series IIx!


keyboard connector (on CMI-317/CMI-355) pinout:
1: +20V (output, power for Alpha keyboard only)
2: MIDI IN D+ (input, from music keyboard)
3: -20V (output, power for Alpha keyboard only)
4: MIDI IN D- (input, from music keyboard)
5: DGND (signal return)
6: DIN (input, from music and Alpha keyboard)
7: GND (power return)
8: PGND (chassis)
9: KEYB DATA OUT (output, to music keyboard)
The Alpha-keyboard (ANK) normally is connected to the music keyboard (MKB) which, in turn, is connected to the CMI. The Alpha-keyboard can also be directly connected to the CMI. See also MFX keyboard section below for additional re-routing of signals.
Note: This pinout is not compatible with Series IIx!

Preh Alpha-keyboard ("ANK"):
RS232 (8-Bit, 9600Baud, 1 stop Bit) output to DIN of Q133. 68705 microcontroller (6805 EPROM version) on Preh mainboard. Additional voltage regulator board CMI-310 for +5/+12/-12V from +/-20V input. The graphic tablet board is an extended 2-dimensional film resistor with the graphic pen as the voltage probe contact. Analog X/Y-values converted by an ADC (on Preh mainboard) and sent via 6-Byte code.
Code list


SCSI harddisks, SCSI QIC tape drives, floppy drives:
see software chapter



MFX1, MFX2:

Overview:
Based upon the CMI Series III XDR architecture with an extra MFX console keyboard (successor of the "MFX III sound design console"). MFX2 requires 4MB of private RAM for the CMI-41. New color graphics cards (CG1, CG2, CG3). MFX2 has an improved SCSI controller (Turbo-SCSI card, replaces CMI-32) for sustained 16-channel output. Optional waveform accelerator DSP card (DSP96K, for time-dilation/contraction under MDR software).
Starting with MFX2, the waveform supervisor (CMI-41) provides 25 address Bits for the 16-Bit waveform bus, giving a 64MB address space (former ~WAS line used as address Bit 25). The lower 32MB are used for waveform RAM, and the upper 32MB are employed for peripheral devices attached to the waveform bus (e.g. ESP-TS1 and ESP-96K).
New analog channel card (CMI-331) revisions have S&H (sample&hold) electronics to reduce quantization noise (however removing a unique sound quality of the CMI at lower sample-rates).
Software Rev9 (MFX1) to Rev11 (MFX2). "MDR" disk-recorder software running on Waveform Supervisor (CMI-41). Still containing full CMI functionality (running on QASAR + CMI-41). The MFX2 system has its own MDR-DOS filesystem in separate partitions for disk-recorder files.
CMI Series III systems can be upgraded to MFX1/MFX2. Genuine MFX2 machines are housed in a 19" rack tower, with separate bins (with same components as used in the CMI Series III housing, though): "DCCU" digital card cage unit, "ACCU" analog card cage unit, power supply unit.

new boards:

CMI-41 CMI-41 as in CMI Series III but with 4MB PRAM (for MFX2) and upgraded GALs (KMON20 Rev8.05 firmware for MFX2)
ESP-CG1 color graphics card (512x256, type 'C', for MFX1)
ESP-CG2 color graphics card (512x512, type 'D', for MFX1 + MFX2)
ESP-CG3 color graphics card (512x512, type 'D', equivalent to latest CG2 revision, for MFX1 + MFX2 + MFX3)
CMI-VID real-panel converter board to analog VGA, for ESP-CG3
ESP-TS1 SCSI controller card ("Turbo-SCSI", "TSCSI", NCR 53C94 Fast SCSI controller (including DMA controller), 16-Bit data Bus, 512KB/2MB buffer WRAM, fast DMA address counter (proprietary), channel support hardware (see CMI-32), QASAR+waveform Bus peripheral, replaces CMI-32, requires revision of CMI-41 and CMI-35, MFX2)
ESP-96K Waveform Accelerator DSP card (also "DSP96K" or "DSP-96K", Motorola XC96002RC40 @40MHz 32Bit floating-point DSP, 128/256KB/1MB private SRAM, 1/2/4/8MB WRAM, two internal 32Bit data and address Busses (A,B), OnCE socket, optional expansion port, waveform Bus peripheral, MFX2 option for time-dilation/contraction)
ESP-348+349 see Series III (MFX1 + MFX2)
ESP-350 AES upgrade daughter board for ESP-348 (CS8402 AES/EBU transmitter, MFX2)
ESP-RT2 improved ESP-RT1 with selectable output re-mapping, see also Series III
CMI-399 S&H upgrade daughter board for CMI-331 Rev1 (2x HA5320), see also Series III
CMI-331 Rev2 new CMI-331 revision (S&H circuits on-board: 2xHA5320, no XLR channel output jacks, to be used with ESP-RTx, MFX2)
CMI-354 see Series III
CMI-355 see Series III



Color graphics cards CG1 (Type C), CG2/CG3 (Type D):

The CG1 (type C) card has a visible resolution of 512(h)x256(v) pixels (like the Q219=type M, see above), whereas the CG2/CG3 (type D) card has 512(h)x512(v) pixels. The video SRAM ("VRAM") has 8 planes, i.e. 8 Bits per pixel. Hence, the VRAM has a size of 128/256KB for type C/D cards (with 8x8=64Bit access port on the type D card). Under CMI/MDR software, the upper Bit of the pixel value is inverted under the cursor pattern.
The 8-Bit pixel color value is fed into a color palette which generates 2+2+2 Bits R+G+B color output, i.e. providing 64 colors. In type C cards, this is accomplished by a PAL with a fixed color mapping. In the case of type D cards, an SRAM ("PALRAM") is used to freely map the 8-Bit pixel color to an 8-Bit
color output: 2+2+2 Bits R+G+B plus 1 Bit "shadow effect". Apart from the 8-Bit pixel color input, the PALRAM has 5 additional input Bits called "attributes" (odd pixel, lower 384 lines, odd line, flash generator, halftone) which provide a variety of color-effects. Hence, the PALRAM has 13 address lines, giving 8KB PALRAM (of which 4KB are effectively used).
Three different color maps are provided for the modes: "MDR", "OSK", "CMI". Type D cards therefore contain three PALRAMs, whereas the type C PAL has three hard-coded color schemes. (With the "palram -d" command, a "type C"-like color-mapping can be loaded into a type D card PALRAM. The cmi/mdr display pages "pal" and "ped" (Rev11) can be used to view and edit the PALRAM. In Rev11, a PALRAM image-file "system.pal" is used.)
A direct access to the VRAM planes and the 3 PALRAMs (type D only) is provided by selectable mappings to the QASAR address region $8000-$BFFF. Furthermore, vector-drawing accelerator functions (which are compatible with the Q219 "type M" monochrome card, extended to 512 lines with the type D card) are implemented. With the color cards, a color-plane access-mask (8-Bit register) defines which Bit-plane (and which VRAM-half for type D cards) within the VRAM is subject to modifications.
Apart from the type M-compatible vertical scrolling of all 8 planes, the color cards additionally offer horizontal scrolling for 2 planes. This is used for real-time waveform scrolling under MDR.
Type C/D cards lack the lightpen logic found on type M cards. (However, the lightpen is not used with the CMI Series III and MFX1/2 software.)

Type D cards provide three output modes:

Mode Resolution Scan rates
0: lowres 512(h)x256(v)
upper 256 lines
50.59Hz(v)
15.43kHz(h)
10MHz(dot clock)
1: double scan 512(h)x256(v)
upper 256 lines doubled
56.94Hz(v)
30.86kHz(h)
20MHz(dot clock)
2: hires 512(h)x512(v)
56.94Hz(v)
30.86kHz(h)
20MHz(dot clock)
Note: Mode 1 is used by QASAR firmware (Q9F0MRK17, F8LMRK17) as default. Mode 2 output signals are compatible with Mode 1. Mode 0 is compatible with type M/C cards.

EGA TTL 64-color output (2+2+2 Bits R+G+B):
1: GND
2: VSYNC
3: HSYNC
4: R2
5: R
6: G
7: G2
8: B
9: B2
10: +5V (with 1A fuse)
Note: rear-panel converter board to analog VGA (CMI-VID)

Color graphics cards (type C/D) require Rev9 and higher software revisions (and updated QASAR and Waveform Supervisor firmware, e.g. Q9F0MRK17 + F8LMRK17 + KMON20 Rev8.05). On the other hand, color graphic cards are necessary for MFX1/MFX2 MDR operation and are supported by the "multi-mode" versions of IOPACK (text console). The "palram" OS-9 program and the "ped" display page can be used to set PALRAM color maps.


TurboSCSI ESP-TS1 ("TSCSI"):
Waveform-Bus Byte-addresses (add 02000000 for WS address!):
03800000-039FFFFF: TSCSI WRAM (max. 2MB)
03C00000-03C0001F: NCR53C94 control
03C00020-03C00023: write: TSCSI DMA start address/2 (i.e. for word)
03F00001: read: status, write: control
Note: For data transfers to/from WRAM (esp. TSCSI on-board WRAM), the TSCSI DMA logic is employed. The TSCSI on-board WRAM is used by the TSCSI driver (with WS DMA channel 3) as a temporary buffer for data transfers to/from WS PRAM and QASAR address space (i.e. spaces which are not accessible from the TSCSI which is a waveform-Bus peripheral device).

status Byte read:
Bit7,Bit6: hardware protection level (00=A, 01=B), MFX2: B

PALs:
CSBOARD: channel support address decoder
CSDEC: channel support address decoder
CSCARD: channel support CC select
TSCLAT (2x): waveform bus control latch
TSWFM1: waveform bus interface
TSWFM2: waveform bus interface
TSDRAM: WRAM signals
TSSCSI: control
TSDMA (5x): DMA logic

ESP-TS1 LEDs:
from top to bottom:
1: ACCESS
2: VTERM (termination voltage present)
3: INT OK
4: RESET


waveform accelerator ESP-96K ("DSP96K"):
Waveform-Bus Byte-addresses (add 02000000 for WS address!):
card ID 0:
00000000-007FFFFF: DSP96K WRAM (max. 8MB)
03400000-034FFFFF: control
card ID 1:
00800000-00FFFFFF: DSP96K WRAM (max. 8MB)
03500000-035FFFFF: control
card ID 2:
02000000-027FFFFF: DSP96K WRAM (max. 8MB)
03600000-036FFFFF: control
card ID 3 (default):
02800000-02FFFFFF: DSP96K WRAM (max. 8MB)
03700000-037FFFFF: control

* Byte read from control start+0:
Bit7: card present
Bit6: extension port sense
Bit5,Bit4: WRAM size
Bit3-0: irrelevant
* Byte read fom control start+1:
reset DSP (set RESET), value irrelevant
* Byte written to control start+1:
start DSP (clear RESET), value irrelevant

address spaces (boot mode 5, 32-Bit addresses, DSP96K private):
Program memory space:
00000000-0000003F: DSP on-chip bootstrap ROM (read-only at RESET)
00000000-000003FF: DSP on-chip program RAM (write-only at RESET)
00000000-000003FF: DSP on-chip program RAM (r/w after RESET)
00000400-FFFFFFFF: external port B
X data memory space:
00000000-000001FF: DSP on-chip X data RAM
00000200-000003FF: N.A.
00000400-000007FF: DSP on-chip X data ROM
00000800-FFFFFF7F: external port A
FFFFFF80-FFFFFFFF: DSP on-chip I/O peripherals
Y data memory space:
00000000-000001FF: DSP on-chip Y data RAM
00000200-000003FF: N.A.
00000400-000007FF: DSP on-chip Y data ROM
00000800-FFFFFFFF: external port B
external port A:
00000000-7FFFFFFF: DSP-96K SRAM bank A
external port B:
00000000-7FFFFFFF: DSP-96K SRAM bank B
82000000-82FFFFFF: DSP-96K WRAM
FFFF0000-FFFF03FF: read: DSP-96K DSPINIT PROM
FFFFFFF0-FFFFFFF3: write: DSP-96K control
Note: DSPINIT PROM is loaded (Bytes, little-endian) to program RAM at 00000000 on RESET.
Note: Byte-order from WFM-Bus to DSP96K 32-Bit WRAM is matched such that WS and DSP96K are able to transfer 32-Bit data words without conversion.

PALs:
DSPCTRL: control
DSPDBUS: bus B control
DSPDACC: DSP WRAM access
DSPWACC: waveform bus WRAM access
DSPWDEC: waveform bus address decoder
DSPWRAM: WRAM signals
DSPTGEN: WRAM timing
DSPONCE: OnCE port

ESP-96K LEDs:
from top to bottom:
1: RESET
2: IRQ
3: WACC (WRAM access from WFM bus)
4: DACC (WRAM access from DSP)
5: BTS (DSP bus B transfer)
6: ATS (DSP bus A transfer)
7: LED1 (spare)
8: LED0 (spare)


MFX console keyboard:


"old MFX" = MFX III sound design console (generation 0)
"new MFX" = MFX1/MFX2/MFX3 console (generation 1)

boards:

MFX010 MFX controller mainboard (68000 @10MHz ("MFX master CPU"), trigger-key scanner ("MFX slave CPU"): 68B09 or 63B09 @2MHz)
MFX020??? old MFX: Mode/transport-keys board (two separate SMPTE displays, one 2x40 LCD display)
MFX030 QWERTY + track/trigger-keys board
MFX040 new MFX: Mode/transport keys board (two 2x40 LCD displays)

Note:
* Old MFX: the 24 trigger-keys are velocity-sensitive
(via 24 Hall sensors). The trigger-key scanning and velocity detection is done by the "MFX slave CPU" (63B09). Power supply via CMI.
* New MFX: MFX slave logic missing, the track/trigger-keys are not velocity-sensitive anymore and are scanned by the "MFX master CPU" (68000). New mode/transport section (esp. different displays). Own built-in switching mode power supply.

MFX Inputs/Ouputs:
The MFX mainboard contains four DUARTS (68681), offering 8 serial inputs and 8 serial outputs (and various parallel I/O ports). A subset of these serial ports is connected to the CMI mainframe (requiring a new rear-panel assembly: CMI-354/355).
CMI -> MFX:
* CMI MIDI D output
* CMI PRINTER2 output (now called "/mfx" under OS9)
* MIDI from CMI music-keyboard (via CMI rear-panel)
* RS232 from Music+Alpha-keyboard (via CMI rear-panel)
MFX -> CMI:
* CMI MIDI D input
* "DIN" Q133 RS232 input
* RS422 I/O (via CMI rear-panel)
Without the MFX keyboard connected, the RS232 from the Music+Alpha-keyboard is directly routed to the RS232 "DIN" input of the Q133. Furthermore, the MIDI output from the Music-keyboard is directly routed to the MIDI D input of the CMI. This re-routing establishes the original CMI routing (see above) and is accomplished by a relay on the CMI rear-panel.
The MFX keyboard sends real-time, timecode, SysEx control commands and forwarded music-keyboard MIDI packets to the CMI MIDI D input. Here, MDR commands are encapsulated within special SysEx packets. In return, the CMI replies or requests MFX services via its PRINTER2 output to the MFX (especially for downloading new application software "mfx.runtime" to the MFX).
Optionally, a CMI music-keyboard and/or an Alpha-keyboard can still be used (attached to the CMI mainframe). In this case, their output signals is re-routed to the MFX (via the CMI rear-panel see above), which in turn multiplexes these signals with its own outputs (in its software "mfx.runtime") to the corresponding CMI mainframe inputs (MIDI D input and "DIN" Q133 RS232 input). (Note: mfx.runtime only supports 3-Byte MIDI command packets from the MIDI-keyboard input, as sent by the CMI music-keyboard. No Real-time, Active-Sensing, SysEx, or omitted start-bytes are allowed.)
The MFX mouse port (RS232, 1200Baud) is used as a replacement for the graphics-pen of the Alpha-keyboard. (Supported protocols: Microsoft 2-button 3-Byte protocol, MouseSystems 3-button 5-Byte protocol, ...) Here, the MFX generates an output stream compatible with the Alpha-keyboard graphics-pen protocol.
See software section below for more information about MFX and MDR.

MFX system:
The 68000 ("MFX master CPU") part of the MFX contains a 64KB firmware ROM, 128KB SRAM (old MFX: 64KB), 96KB NVRAM (with battery backup, old MFX: 32KB). The NVRAM contains the MFX application software "mfx.runtime", which is loaded to the SRAM and started by the firmware on reboot. New application software can also be downloaded from the CMI (via the CMI PRINTER2="/mfx" port).
The 6809/6309 ("MFX slave CPU") in older MFX versions ("MFX III sound design console") is solely used for scanning and velocity-detection of the 24 track/trigger keys (intended as "sound event trigger keys"). Communication between the 68000 and the 6809/6309 is accomplished by a FIFO (slave to master) and a VIA chip (6522). In later versions (MFX1/MFX2), the 68000 is used also for track/trigger key scanning (not velocity sensitive anymore, though), primarily used as track keys under MDR (but also for triggering samples under the CMI-control MFX-page).

68000 "MFX master CPU" address space:
000000: RAM (64KB 2x62256) or mapped to ROM if OVLY
100000: ROM (64KB 2x27C256)
200000: new MFX: expansion RAM (64KB 2x62256)
300000: new MFX: expansion NVRAM (64KB 2x62256)
400000: LEDs (COL)
500000: key/expansion port switches input (SWITCH, SWO0...7)
600000: FIFO (HDATA/IRQ6, from 6309/6809)
700000: watchdog
800000: NVRAM (32KB 1x62256, odd addresses only)
900000: DUART "ACIA5" (ACIA1/IRQ5 68681):
. SA: MIDI
. SB: MIDI
. IP: Fader ADC (INTR=FR), VIA (CA1=DT)
. OP: key switches (SWI0...3, ENQUERTY, ENPANEL)
a00000: DUART "ACIA4" (ACIA2/IRQ4 68681):
. SA: RS422
. SB: expansion port
. IP: jogger (JOG1,JOG2), LEDs (CHECK), SYSC
. OP: speaker (SL1...5), SCON, EXCON, VIA (CA2=DR)
b00000: DUART "ACIA3" (ACIA3/IRQ3 68281):
. SA: RS232
. SB: RS232
. IP: Bus-Mouse (MC1...4,MB1,MB2)
. OP: VIA to 6309/6809 (TH0...7)
c00000: DUART "ACIA2" (ACIA4/IRQ2 68681):
. SA: Mouse
. SB: debug port
. IP: IRQ6
. OP: expansion port switches (SW0OUT...SW2OUT), OVLY, FIFOR
d00000: N.C.
e00000: Fader 8-channel ADC (FAD)
e40000: N.C.
e80000: new MFX: LCD 1 (DIS1)
ec0000: new MFX: LCD 2 (DIS2)
f00000: N.C.

6309/6809 "MFX slave CPU" address space:
0000: RAM (8KB 6264)
2000: N.C.
4000: Hall-sensor-DAC
6000: Hall-sensor-ADC
8000: FIFO (SEND09, to 68000)
a000: VIA (6522)
e000: ROM (8KB 27C64)




Horizontal Productions

replacement parts, repairs, upgrades, software, libraries,...

WFM32: 32MB waveform memory board (replaces all CMI-xx waveform memory boards), for CMI Series III/MFX1/MFX2 with CMI-41 (can also be used with CMI-33, but then only 14MB available)
 
 
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Designed by K.M. Indlekofer. See disclaimer. Send comments about this site to Klaus Michael Indlekofer. Last updated 07/24/2005.